net/sfc: fix align to power of 2 when align has smaller type

[dpdk.git] / drivers / net / sfc / base / siena_nic.c

diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c
index 0d6d071..7ba595b 100644 (file)
--- a/drivers/net/sfc/base/siena_nic.c
+++ b/drivers/net/sfc/base/siena_nic.c
@@ -18,11 +18,10 @@ siena_nic_get_partn_mask(
        __out                   unsigned int *maskp)
 {
        efx_mcdi_req_t req;
-       uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN,
-                           MC_CMD_NVRAM_TYPES_OUT_LEN)];
+       EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_TYPES_IN_LEN,
+               MC_CMD_NVRAM_TYPES_OUT_LEN);
        efx_rc_t rc;
 
-       (void) memset(payload, 0, sizeof (payload));
        req.emr_cmd = MC_CMD_NVRAM_TYPES;
        req.emr_in_buf = payload;
        req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
@@ -105,6 +104,10 @@ siena_board_cfg(
        encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
                FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
+       encp->enc_ev_desc_size = SIENA_EVQ_DESC_SIZE;
+       encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE;
+       encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;
+
        /* When hash header insertion is enabled, Siena inserts 16 bytes */
        encp->enc_rx_prefix_size = 16;
 
@@ -115,11 +118,22 @@ siena_board_cfg(
        /* Alignment for WPTR updates */
        encp->enc_rx_push_align = 1;
 
+#if EFSYS_OPT_RX_SCALE
        /* There is one RSS context per function */
        encp->enc_rx_scale_max_exclusive_contexts = 1;
 
+       encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR);
+       encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ);
+
+       /*
+        * It is always possible to use port numbers
+        * as the input data for hash computation.
+        */
+       encp->enc_rx_scale_l4_hash_supported = B_TRUE;
+
        /* There is no support for additional RSS modes */
        encp->enc_rx_scale_additional_modes_supported = B_FALSE;
+#endif /* EFSYS_OPT_RX_SCALE */
 
        encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
        /* Fragments must not span 4k boundaries. */
@@ -139,7 +153,14 @@ siena_board_cfg(
        encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
        encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
 
-       encp->enc_txq_max_ndescs = 4096;
+       encp->enc_evq_max_nevs = SIENA_EVQ_MAXNEVS;
+       encp->enc_evq_min_nevs = SIENA_EVQ_MINNEVS;
+
+       encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
+       encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
+
+       encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
+       encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;
 
        encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
            (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
@@ -152,6 +173,7 @@ siena_board_cfg(
        encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
        encp->enc_rx_packed_stream_supported = B_FALSE;
        encp->enc_rx_var_packed_stream_supported = B_FALSE;
+       encp->enc_rx_es_super_buffer_supported = B_FALSE;
        encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
 
        /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
@@ -162,6 +184,10 @@ siena_board_cfg(
 
        encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
 
+       encp->enc_filter_action_flag_supported = B_FALSE;
+       encp->enc_filter_action_mark_supported = B_FALSE;
+       encp->enc_filter_action_mark_max = 0;
+
        return (0);
 
 fail2: