-/*-
- * Copyright (c) 2016 Solarflare Communications Inc.
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2016-2018 Solarflare Communications Inc.
* All rights reserved.
*
* This software was jointly developed between OKTET Labs (under contract
* for Solarflare) and Solarflare Communications, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SFC_COMMON_EFSYS_H
#include <rte_common.h>
#include <rte_malloc.h>
#include <rte_log.h>
+#include <rte_io.h>
#include "sfc_debug.h"
+#include "sfc_log.h"
#ifdef __cplusplus
extern "C" {
#define __out_ecount_opt(_n)
#define __out_bcount(_n)
#define __out_bcount_opt(_n)
+#define __out_bcount_part(_n, _l)
+#define __out_bcount_part_opt(_n, _l)
#define __deref_out
/* Code inclusion options */
-#define EFSYS_OPT_NAMES 0
+#define EFSYS_OPT_NAMES 1
/* Disable SFN5xxx/SFN6xxx since it requires specific support in the PMD */
#define EFSYS_OPT_SIENA 0
#define EFSYS_OPT_HUNTINGTON 1
/* Enable SFN8xxx support */
#define EFSYS_OPT_MEDFORD 1
+/* Enable SFN2xxx support */
+#define EFSYS_OPT_MEDFORD2 1
#ifdef RTE_LIBRTE_SFC_EFX_DEBUG
#define EFSYS_OPT_CHECK_REG 1
#else
/* MCDI is required for SFN7xxx and SFN8xx */
#define EFSYS_OPT_MCDI 1
#define EFSYS_OPT_MCDI_LOGGING 1
-#define EFSYS_OPT_MCDI_PROXY_AUTH 0
+#define EFSYS_OPT_MCDI_PROXY_AUTH 1
-#define EFSYS_OPT_MAC_STATS 0
+#define EFSYS_OPT_MAC_STATS 1
#define EFSYS_OPT_LOOPBACK 0
#define EFSYS_OPT_VPD 0
#define EFSYS_OPT_NVRAM 0
#define EFSYS_OPT_BOOTCFG 0
+#define EFSYS_OPT_IMAGE_LAYOUT 0
#define EFSYS_OPT_DIAG 0
-#define EFSYS_OPT_RX_SCALE 0
+#define EFSYS_OPT_RX_SCALE 1
#define EFSYS_OPT_QSTATS 0
/* Filters support is required for SFN7xxx and SFN8xx */
#define EFSYS_OPT_FILTER 1
#define EFSYS_OPT_RX_PACKED_STREAM 0
+#define EFSYS_OPT_TUNNEL 1
+
/* ID */
typedef struct __efsys_identifier_s efsys_identifier_t;
/* DMA */
-typedef phys_addr_t efsys_dma_addr_t;
+typedef rte_iova_t efsys_dma_addr_t;
typedef struct efsys_mem_s {
const struct rte_memzone *esm_mz;
} while (B_FALSE)
+#define EFSYS_MEM_SIZE(_esmp) \
+ ((_esmp)->esm_mz->len)
+
#define EFSYS_MEM_ADDR(_esmp) \
((_esmp)->esm_addr)
\
_addr = (volatile uint32_t *)(_base + (_offset)); \
rte_rmb(); \
- (_edp)->ed_u32[0] = _addr[0]; \
+ (_edp)->ed_u32[0] = rte_read32_relaxed(_addr); \
\
EFSYS_PROBE2(bar_readd, unsigned int, (_offset), \
uint32_t, (_edp)->ed_u32[0]); \
\
_addr = (volatile uint64_t *)(_base + (_offset)); \
rte_rmb(); \
- (_eqp)->eq_u64[0] = _addr[0]; \
+ (_eqp)->eq_u64[0] = rte_read64_relaxed(_addr); \
\
EFSYS_PROBE3(bar_readq, unsigned int, (_offset), \
uint32_t, (_eqp)->eq_u32[1], \
\
_addr = (volatile __m128i *)(_base + (_offset)); \
rte_rmb(); \
+ /* There is no rte_read128_relaxed() yet */ \
(_eop)->eo_u128[0] = _addr[0]; \
\
EFSYS_PROBE5(bar_reado, unsigned int, (_offset), \
uint32_t, (_edp)->ed_u32[0]); \
\
_addr = (volatile uint32_t *)(_base + (_offset)); \
- _addr[0] = (_edp)->ed_u32[0]; \
+ rte_write32_relaxed((_edp)->ed_u32[0], _addr); \
rte_wmb(); \
\
_NOTE(CONSTANTCONDITION); \
uint32_t, (_eqp)->eq_u32[0]); \
\
_addr = (volatile uint64_t *)(_base + (_offset)); \
- _addr[0] = (_eqp)->eq_u64[0]; \
+ rte_write64_relaxed((_eqp)->eq_u64[0], _addr); \
rte_wmb(); \
\
SFC_BAR_UNLOCK(_esbp); \
uint32_t, (_eop)->eo_u32[0]); \
\
_addr = (volatile __m128i *)(_base + (_offset)); \
+ /* There is no rte_write128_relaxed() yet */ \
_addr[0] = (_eop)->eo_u128[0]; \
rte_wmb(); \
\
/* BARRIERS */
#define EFSYS_MEM_READ_BARRIER() rte_rmb()
-#define EFSYS_PIO_WRITE_BARRIER() rte_wmb()
+#define EFSYS_PIO_WRITE_BARRIER() rte_io_wmb()
/* DMA SYNC */
*/
#define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size) ((void)0)
-#define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) ((void)0)
+
+/* Just avoid store and compiler (impliciltly) reordering */
+#define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) rte_wmb()
/* TIMESTAMP */
#define EFSYS_ERR(_esip, _code, _dword0, _dword1) \
do { \
(void)(_esip); \
- RTE_LOG(ERR, PMD, "FATAL ERROR #%u (0x%08x%08x)\n", \
+ SFC_GENERIC_LOG(ERR, "FATAL ERROR #%u (0x%08x%08x)", \
(_code), (_dword0), (_dword1)); \
_NOTE(CONSTANTCONDITION); \
} while (B_FALSE)
git.droids-corp.org / dpdk.git / blobdiff