#include "efx_regs_ef100.h"
#include "efx.h"
+#include "sfc.h"
#include "sfc_debug.h"
+#include "sfc_flow_tunnel.h"
#include "sfc_tweak.h"
#include "sfc_dp_rx.h"
#include "sfc_kvargs.h"
#include "sfc_ef100.h"
+#include "sfc_nic_dma_dp.h"
#define sfc_ef100_rx_err(_rxq, ...) \
#define SFC_EF100_RXQ_USER_MARK 0x20
#define SFC_EF100_RXQ_FLAG_INTR_EN 0x40
#define SFC_EF100_RXQ_INGRESS_MPORT 0x80
+#define SFC_EF100_RXQ_USER_FLAG 0x100
+#define SFC_EF100_RXQ_NIC_DMA_MAP 0x200
unsigned int ptr_mask;
unsigned int evq_phase_bit_shift;
unsigned int ready_pkts;
uint64_t rearm_data;
uint16_t buf_size;
uint16_t prefix_size;
+ uint32_t user_mark_mask;
unsigned int evq_hw_index;
volatile void *evq_prime;
/* Datapath receive queue anchor */
struct sfc_dp_rxq dp;
+
+ const struct sfc_nic_dma_info *nic_dma_info;
};
static inline struct sfc_ef100_rxq *
* operations that follow it (i.e. doorbell write).
*/
rte_write32(dword.ed_u32[0], rxq->doorbell);
- rxq->dp.dpq.rx_dbells++;
+ rxq->dp.dpq.dbells++;
sfc_ef100_rx_debug(rxq, "RxQ pushed doorbell at pidx %u (added=%u)",
EFX_DWORD_FIELD(dword, ERF_GZ_RX_RING_PIDX),
SFC_ASSERT(bulks > 0);
do {
- unsigned int id;
unsigned int i;
if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
break;
}
- for (i = 0, id = added & ptr_mask;
- i < RTE_DIM(objs);
- ++i, ++id) {
+ for (i = 0; i < RTE_DIM(objs); ++i) {
struct rte_mbuf *m = objs[i];
struct sfc_ef100_rx_sw_desc *rxd;
- rte_iova_t phys_addr;
+ rte_iova_t dma_addr;
__rte_mbuf_raw_sanity_check(m);
- SFC_ASSERT((id & ~ptr_mask) == 0);
- rxd = &rxq->sw_ring[id];
+ dma_addr = rte_mbuf_data_iova_default(m);
+ if (rxq->flags & SFC_EF100_RXQ_NIC_DMA_MAP) {
+ dma_addr = sfc_nic_dma_map(rxq->nic_dma_info,
+ dma_addr,
+ rte_pktmbuf_data_len(m));
+ if (unlikely(dma_addr == RTE_BAD_IOVA)) {
+ sfc_ef100_rx_err(rxq,
+ "failed to map DMA address on Rx");
+ /* Just skip buffer and try to continue */
+ rte_mempool_put(rxq->refill_mb_pool, m);
+ continue;
+ }
+ }
+
+ rxd = &rxq->sw_ring[added & ptr_mask];
rxd->mbuf = m;
/*
* structure members.
*/
- phys_addr = rte_mbuf_data_iova_default(m);
- EFX_POPULATE_QWORD_1(rxq->rxq_hw_ring[id],
- ESF_GZ_RX_BUF_ADDR, phys_addr);
+ EFX_POPULATE_QWORD_1(rxq->rxq_hw_ring[added & ptr_mask],
+ ESF_GZ_RX_BUF_ADDR, dma_addr);
+ added++;
}
-
- added += RTE_DIM(objs);
} while (--bulks > 0);
SFC_ASSERT(rxq->added != added);
return EFX_WORD_FIELD(class,
ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM) ==
ESE_GZ_RH_HCLASS_L4_CSUM_GOOD ?
- PKT_RX_L4_CKSUM_GOOD : PKT_RX_L4_CKSUM_BAD;
+ RTE_MBUF_F_RX_L4_CKSUM_GOOD : RTE_MBUF_F_RX_L4_CKSUM_BAD;
}
static inline uint64_t
return EFX_WORD_FIELD(class,
ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM) ==
ESE_GZ_RH_HCLASS_L4_CSUM_GOOD ?
- PKT_RX_OUTER_L4_CKSUM_GOOD : PKT_RX_OUTER_L4_CKSUM_BAD;
+ RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD : RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
}
static uint32_t
ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS)) {
case ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD:
ptype |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
- *ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ *ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD:
ptype |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
- *ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ *ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP6:
ptype |= RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD:
ptype |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
- *ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
+ *ol_flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP6:
ptype |= RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS)) {
case ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD:
ptype |= RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
- *ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ *ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD:
ptype |= RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
- *ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ *ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP6:
ptype |= RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
EFX_RX_PREFIX_FIELD(INGRESS_MPORT,
ESF_GZ_RX_PREFIX_INGRESS_MPORT, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(RSS_HASH, B_FALSE),
+ SFC_EF100_RX_PREFIX_FIELD(USER_FLAG, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(USER_MARK, B_FALSE),
#undef SFC_EF100_RX_PREFIX_FIELD
if ((rxq->flags & SFC_EF100_RXQ_RSS_HASH) &&
EFX_TEST_XWORD_BIT(rx_prefix[0],
ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN)) {
- ol_flags |= PKT_RX_RSS_HASH;
+ ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
/* EFX_XWORD_FIELD converts little-endian to CPU */
m->hash.rss = EFX_XWORD_FIELD(rx_prefix[0],
ESF_GZ_RX_PREFIX_RSS_HASH);
}
+ if (rxq->flags & SFC_EF100_RXQ_USER_FLAG) {
+ uint32_t user_flag;
+
+ user_flag = EFX_XWORD_FIELD(rx_prefix[0],
+ ESF_GZ_RX_PREFIX_USER_FLAG);
+ if (user_flag != 0)
+ ol_flags |= RTE_MBUF_F_RX_FDIR;
+ }
+
if (rxq->flags & SFC_EF100_RXQ_USER_MARK) {
+ uint8_t ft_ctx_mark;
uint32_t user_mark;
+ uint32_t mark;
/* EFX_XWORD_FIELD converts little-endian to CPU */
- user_mark = EFX_XWORD_FIELD(rx_prefix[0],
- ESF_GZ_RX_PREFIX_USER_MARK);
+ mark = EFX_XWORD_FIELD(rx_prefix[0],
+ ESF_GZ_RX_PREFIX_USER_MARK);
+
+ user_mark = mark & rxq->user_mark_mask;
if (user_mark != SFC_EF100_USER_MARK_INVALID) {
- ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
+ ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
m->hash.fdir.hi = user_mark;
}
+
+ ft_ctx_mark = SFC_FT_FLOW_MARK_TO_CTX_MARK(mark);
+ if (ft_ctx_mark != SFC_FT_CTX_MARK_INVALID) {
+ sfc_ft_ctx_id_t ft_ctx_id;
+
+ ft_ctx_id = SFC_FT_CTX_MARK_TO_CTX_ID(ft_ctx_mark);
+
+ ol_flags |= sfc_dp_ft_ctx_id_valid;
+ *RTE_MBUF_DYNFIELD(m, sfc_dp_ft_ctx_id_offset,
+ sfc_ft_ctx_id_t *) = ft_ctx_id;
+ }
}
if (rxq->flags & SFC_EF100_RXQ_INGRESS_MPORT) {
rxq->max_fill_level = info->max_fill_level;
rxq->refill_threshold = info->refill_threshold;
rxq->prefix_size = info->prefix_size;
+
+ SFC_ASSERT(info->user_mark_mask != 0);
+ rxq->user_mark_mask = info->user_mark_mask;
+
rxq->buf_size = info->buf_size;
rxq->refill_mb_pool = info->refill_mb_pool;
rxq->rxq_hw_ring = info->rxq_hw_ring;
info->fcw_offset +
ER_GZ_EVQ_INT_PRIME_OFST;
+ rxq->nic_dma_info = info->nic_dma_info;
+ if (rxq->nic_dma_info->nb_regions > 0)
+ rxq->flags |= SFC_EF100_RXQ_NIC_DMA_MAP;
+
sfc_ef100_rx_debug(rxq, "RxQ doorbell is %p", rxq->doorbell);
*dp_rxqp = &rxq->dp;
unsup_rx_prefix_fields =
efx_rx_prefix_layout_check(pinfo, &sfc_ef100_rx_prefix_layout);
- /* LENGTH and CLASS filds must always be present */
+ /* LENGTH and CLASS fields must always be present */
if ((unsup_rx_prefix_fields &
((1U << EFX_RX_PREFIX_FIELD_LENGTH) |
(1U << EFX_RX_PREFIX_FIELD_CLASS))) != 0)
else
rxq->flags &= ~SFC_EF100_RXQ_RSS_HASH;
+ if ((unsup_rx_prefix_fields &
+ (1U << EFX_RX_PREFIX_FIELD_USER_FLAG)) == 0)
+ rxq->flags |= SFC_EF100_RXQ_USER_FLAG;
+ else
+ rxq->flags &= ~SFC_EF100_RXQ_USER_FLAG;
+
if ((unsup_rx_prefix_fields &
(1U << EFX_RX_PREFIX_FIELD_USER_MARK)) == 0)
rxq->flags |= SFC_EF100_RXQ_USER_MARK;
.hw_fw_caps = SFC_DP_HW_FW_CAP_EF100,
},
.features = SFC_DP_RX_FEAT_MULTI_PROCESS |
+ SFC_DP_RX_FEAT_FLOW_FLAG |
SFC_DP_RX_FEAT_FLOW_MARK |
SFC_DP_RX_FEAT_INTR |
SFC_DP_RX_FEAT_STATS,
.dev_offload_capa = 0,
- .queue_offload_capa = DEV_RX_OFFLOAD_CHECKSUM |
- DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
- DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
- DEV_RX_OFFLOAD_SCATTER |
- DEV_RX_OFFLOAD_RSS_HASH,
+ .queue_offload_capa = RTE_ETH_RX_OFFLOAD_CHECKSUM |
+ RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
+ RTE_ETH_RX_OFFLOAD_SCATTER |
+ RTE_ETH_RX_OFFLOAD_RSS_HASH,
.get_dev_info = sfc_ef100_rx_get_dev_info,
.qsize_up_rings = sfc_ef100_rx_qsize_up_rings,
.qcreate = sfc_ef100_rx_qcreate,
git.droids-corp.org / dpdk.git / blobdiff