/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
* Copyright(c) 2018-2019 Solarflare Communications Inc.
*
* This software was jointly developed between OKTET Labs (under contract
((_ndesc) - 1 /* head must not step on tail */ - \
1 /* Rx error */ - 1 /* flush */)
+/** Invalid user mark value when the mark should be treated as unset */
+#define SFC_EF100_USER_MARK_INVALID 0
+
struct sfc_ef100_rx_sw_desc {
struct rte_mbuf *mbuf;
};
#define SFC_EF100_RXQ_STARTED 0x1
#define SFC_EF100_RXQ_NOT_RUNNING 0x2
#define SFC_EF100_RXQ_EXCEPTION 0x4
+#define SFC_EF100_RXQ_RSS_HASH 0x10
+#define SFC_EF100_RXQ_USER_MARK 0x20
+#define SFC_EF100_RXQ_FLAG_INTR_EN 0x40
unsigned int ptr_mask;
unsigned int evq_phase_bit_shift;
unsigned int ready_pkts;
unsigned int completed;
unsigned int evq_read_ptr;
+ unsigned int evq_read_ptr_primed;
volatile efx_qword_t *evq_hw_ring;
struct sfc_ef100_rx_sw_desc *sw_ring;
uint64_t rearm_data;
uint16_t buf_size;
uint16_t prefix_size;
+ unsigned int evq_hw_index;
+ volatile void *evq_prime;
+
/* Used on refill */
unsigned int added;
unsigned int max_fill_level;
return container_of(dp_rxq, struct sfc_ef100_rxq, dp);
}
+static void
+sfc_ef100_rx_qprime(struct sfc_ef100_rxq *rxq)
+{
+ sfc_ef100_evq_prime(rxq->evq_prime, rxq->evq_hw_index,
+ rxq->evq_read_ptr & rxq->ptr_mask);
+ rxq->evq_read_ptr_primed = rxq->evq_read_ptr;
+}
+
static inline void
sfc_ef100_rx_qpush(struct sfc_ef100_rxq *rxq, unsigned int added)
{
* operations that follow it (i.e. doorbell write).
*/
rte_write32(dword.ed_u32[0], rxq->doorbell);
+ rxq->dp.dpq.rx_dbells++;
sfc_ef100_rx_debug(rxq, "RxQ pushed doorbell at pidx %u (added=%u)",
EFX_DWORD_FIELD(dword, ERF_GZ_RX_RING_PIDX),
struct sfc_ef100_rx_sw_desc *rxd;
rte_iova_t phys_addr;
- MBUF_RAW_ALLOC_CHECK(m);
+ __rte_mbuf_raw_sanity_check(m);
SFC_ASSERT((id & ~ptr_mask) == 0);
rxd = &rxq->sw_ring[id];
return EFX_WORD_FIELD(class,
ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM) ==
ESE_GZ_RH_HCLASS_L4_CSUM_GOOD ?
- PKT_RX_OUTER_L4_CKSUM_GOOD : PKT_RX_OUTER_L4_CKSUM_GOOD;
+ PKT_RX_OUTER_L4_CKSUM_GOOD : PKT_RX_OUTER_L4_CKSUM_BAD;
}
static uint32_t
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD:
ptype |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
- *ol_flags |= PKT_RX_EIP_CKSUM_BAD;
+ *ol_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
break;
case ESE_GZ_RH_HCLASS_L3_CLASS_IP6:
ptype |= RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
EFX_RX_PREFIX_FIELD(_name, ESF_GZ_RX_PREFIX_ ## _name, _big_endian)
SFC_EF100_RX_PREFIX_FIELD(LENGTH, B_FALSE),
+ SFC_EF100_RX_PREFIX_FIELD(RSS_HASH_VALID, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(CLASS, B_FALSE),
+ SFC_EF100_RX_PREFIX_FIELD(RSS_HASH, B_FALSE),
+ SFC_EF100_RX_PREFIX_FIELD(USER_MARK, B_FALSE),
#undef SFC_EF100_RX_PREFIX_FIELD
}
};
static bool
-sfc_ef100_rx_prefix_to_offloads(const efx_oword_t *rx_prefix,
+sfc_ef100_rx_prefix_to_offloads(const struct sfc_ef100_rxq *rxq,
+ const efx_oword_t *rx_prefix,
struct rte_mbuf *m)
{
const efx_word_t *class;
m->packet_type = sfc_ef100_rx_class_decode(*class, &ol_flags);
+ if ((rxq->flags & SFC_EF100_RXQ_RSS_HASH) &&
+ EFX_TEST_OWORD_BIT(rx_prefix[0],
+ ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN)) {
+ ol_flags |= PKT_RX_RSS_HASH;
+ /* EFX_OWORD_FIELD converts little-endian to CPU */
+ m->hash.rss = EFX_OWORD_FIELD(rx_prefix[0],
+ ESF_GZ_RX_PREFIX_RSS_HASH);
+ }
+
+ if (rxq->flags & SFC_EF100_RXQ_USER_MARK) {
+ uint32_t user_mark;
+
+ /* EFX_OWORD_FIELD converts little-endian to CPU */
+ user_mark = EFX_OWORD_FIELD(rx_prefix[0],
+ ESF_GZ_RX_PREFIX_USER_MARK);
+ if (user_mark != SFC_EF100_USER_MARK_INVALID) {
+ ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
+ m->hash.fdir.hi = user_mark;
+ }
+ }
+
m->ol_flags = ol_flags;
return true;
}
rxq->ready_pkts--;
pkt = sfc_ef100_rx_next_mbuf(rxq);
- MBUF_RAW_ALLOC_CHECK(pkt);
+ __rte_mbuf_raw_sanity_check(pkt);
RTE_BUILD_BUG_ON(sizeof(pkt->rearm_data[0]) !=
sizeof(rxq->rearm_data));
seg_len = RTE_MIN(pkt_len, rxq->buf_size - rxq->prefix_size);
rte_pktmbuf_data_len(pkt) = seg_len;
- deliver = sfc_ef100_rx_prefix_to_offloads(rx_prefix, pkt);
+ deliver = sfc_ef100_rx_prefix_to_offloads(rxq, rx_prefix, pkt);
lastseg = pkt;
while ((pkt_len -= seg_len) > 0) {
struct rte_mbuf *seg;
seg = sfc_ef100_rx_next_mbuf(rxq);
- MBUF_RAW_ALLOC_CHECK(seg);
+ __rte_mbuf_raw_sanity_check(seg);
seg->data_off = RTE_PKTMBUF_HEADROOM;
/* It is not a problem if we refill in the case of exception */
sfc_ef100_rx_qrefill(rxq);
+ if ((rxq->flags & SFC_EF100_RXQ_FLAG_INTR_EN) &&
+ rxq->evq_read_ptr_primed != rxq->evq_read_ptr)
+ sfc_ef100_rx_qprime(rxq);
+
done:
return nb_pkts - (rx_pkts_end - rx_pkts);
}
ER_GZ_RX_RING_DOORBELL_OFST +
(info->hw_index << info->vi_window_shift);
+ rxq->evq_hw_index = info->evq_hw_index;
+ rxq->evq_prime = (volatile uint8_t *)info->mem_bar +
+ info->fcw_offset +
+ ER_GZ_EVQ_INT_PRIME_OFST;
+
sfc_ef100_rx_debug(rxq, "RxQ doorbell is %p", rxq->doorbell);
*dp_rxqp = &rxq->dp;
(1U << EFX_RX_PREFIX_FIELD_CLASS))) != 0)
return ENOTSUP;
+ if ((unsup_rx_prefix_fields &
+ ((1U << EFX_RX_PREFIX_FIELD_RSS_HASH_VALID) |
+ (1U << EFX_RX_PREFIX_FIELD_RSS_HASH))) == 0)
+ rxq->flags |= SFC_EF100_RXQ_RSS_HASH;
+ else
+ rxq->flags &= ~SFC_EF100_RXQ_RSS_HASH;
+
+ if ((unsup_rx_prefix_fields &
+ (1U << EFX_RX_PREFIX_FIELD_USER_MARK)) == 0)
+ rxq->flags |= SFC_EF100_RXQ_USER_MARK;
+ else
+ rxq->flags &= ~SFC_EF100_RXQ_USER_MARK;
+
rxq->prefix_size = pinfo->erpl_length;
rxq->rearm_data = sfc_ef100_mk_mbuf_rearm_data(rxq->dp.dpq.port_id,
rxq->prefix_size);
rxq->flags |= SFC_EF100_RXQ_STARTED;
rxq->flags &= ~(SFC_EF100_RXQ_NOT_RUNNING | SFC_EF100_RXQ_EXCEPTION);
+ if (rxq->flags & SFC_EF100_RXQ_FLAG_INTR_EN)
+ sfc_ef100_rx_qprime(rxq);
+
return 0;
}
rxq->flags &= ~SFC_EF100_RXQ_STARTED;
}
+static sfc_dp_rx_intr_enable_t sfc_ef100_rx_intr_enable;
+static int
+sfc_ef100_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
+{
+ struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
+
+ rxq->flags |= SFC_EF100_RXQ_FLAG_INTR_EN;
+ if (rxq->flags & SFC_EF100_RXQ_STARTED)
+ sfc_ef100_rx_qprime(rxq);
+ return 0;
+}
+
+static sfc_dp_rx_intr_disable_t sfc_ef100_rx_intr_disable;
+static int
+sfc_ef100_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
+{
+ struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
+
+ /* Cannot disarm, just disable rearm */
+ rxq->flags &= ~SFC_EF100_RXQ_FLAG_INTR_EN;
+ return 0;
+}
+
+static sfc_dp_rx_get_pushed_t sfc_ef100_rx_get_pushed;
+static unsigned int
+sfc_ef100_rx_get_pushed(struct sfc_dp_rxq *dp_rxq)
+{
+ struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
+
+ /*
+ * The datapath keeps track only of added descriptors, since
+ * the number of pushed descriptors always equals the number
+ * of added descriptors due to enforced alignment.
+ */
+ return rxq->added;
+}
+
struct sfc_dp_rx sfc_ef100_rx = {
.dp = {
.name = SFC_KVARG_DATAPATH_EF100,
.type = SFC_DP_RX,
.hw_fw_caps = SFC_DP_HW_FW_CAP_EF100,
},
- .features = SFC_DP_RX_FEAT_MULTI_PROCESS,
+ .features = SFC_DP_RX_FEAT_MULTI_PROCESS |
+ SFC_DP_RX_FEAT_INTR,
.dev_offload_capa = 0,
.queue_offload_capa = DEV_RX_OFFLOAD_CHECKSUM |
DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
- DEV_RX_OFFLOAD_SCATTER,
+ DEV_RX_OFFLOAD_SCATTER |
+ DEV_RX_OFFLOAD_RSS_HASH,
.get_dev_info = sfc_ef100_rx_get_dev_info,
.qsize_up_rings = sfc_ef100_rx_qsize_up_rings,
.qcreate = sfc_ef100_rx_qcreate,
.supported_ptypes_get = sfc_ef100_supported_ptypes_get,
.qdesc_npending = sfc_ef100_rx_qdesc_npending,
.qdesc_status = sfc_ef100_rx_qdesc_status,
+ .intr_enable = sfc_ef100_rx_intr_enable,
+ .intr_disable = sfc_ef100_rx_intr_disable,
+ .get_pushed = sfc_ef100_rx_get_pushed,
.pkt_burst = sfc_ef100_recv_pkts,
};
git.droids-corp.org / dpdk.git / blobdiff