/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
* Copyright(c) 2016-2019 Solarflare Communications Inc.
*
* This software was jointly developed between OKTET Labs (under contract
struct sfc_ef10_rx_sw_desc *rxd;
rte_iova_t phys_addr;
- MBUF_RAW_ALLOC_CHECK(m);
+ __rte_mbuf_raw_sanity_check(m);
SFC_ASSERT((id & ~ptr_mask) == 0);
rxd = &rxq->sw_ring[id];
SFC_ASSERT(rxq->added != added);
rxq->added = added;
- sfc_ef10_rx_qpush(rxq->doorbell, added, ptr_mask);
+ sfc_ef10_rx_qpush(rxq->doorbell, added, ptr_mask, &rxq->dp.dpq.dbells);
}
static void
return rx_pkts;
}
+/*
+ * Below Rx pseudo-header (aka Rx prefix) accessors rely on the
+ * following fields layout.
+ */
+static const efx_rx_prefix_layout_t sfc_ef10_rx_prefix_layout = {
+ .erpl_fields = {
+ [EFX_RX_PREFIX_FIELD_RSS_HASH] =
+ { 0, sizeof(uint32_t) * CHAR_BIT, B_FALSE },
+ [EFX_RX_PREFIX_FIELD_LENGTH] =
+ { 8 * CHAR_BIT, sizeof(uint16_t) * CHAR_BIT, B_FALSE },
+ }
+};
static uint16_t
sfc_ef10_rx_pseudo_hdr_get_len(const uint8_t *pseudo_hdr)
{
rxd = &rxq->sw_ring[pending++ & ptr_mask];
m = rxd->mbuf;
- MBUF_RAW_ALLOC_CHECK(m);
+ __rte_mbuf_raw_sanity_check(m);
m->data_off = RTE_PKTMBUF_HEADROOM;
rte_pktmbuf_data_len(m) = seg_len;
/* Mask RSS hash offload flag if RSS is not enabled */
sfc_ef10_rx_ev_to_offloads(rx_ev, m,
(rxq->flags & SFC_EF10_RXQ_RSS_HASH) ?
- ~0ull : ~PKT_RX_RSS_HASH);
+ ~0ull : ~RTE_MBUF_F_RX_RSS_HASH);
/* data_off already moved past pseudo header */
pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
/*
* Always get RSS hash from pseudo header to avoid
* condition/branching. If it is valid or not depends on
- * PKT_RX_RSS_HASH in m->ol_flags.
+ * RTE_MBUF_F_RX_RSS_HASH in m->ol_flags.
*/
m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
/*
* Always get RSS hash from pseudo header to avoid
* condition/branching. If it is valid or not depends on
- * PKT_RX_RSS_HASH in m->ol_flags.
+ * RTE_MBUF_F_RX_RSS_HASH in m->ol_flags.
*/
m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
if (info->rxq_entries != info->evq_entries)
goto fail_rxq_args;
+ rc = ENOTSUP;
+ if (info->nic_dma_info->nb_regions > 0)
+ goto fail_nic_dma;
+
rc = ENOMEM;
rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
RTE_CACHE_LINE_SIZE, socket_id);
rte_free(rxq);
fail_rxq_alloc:
+fail_nic_dma:
fail_rxq_args:
return rc;
}
static sfc_dp_rx_qstart_t sfc_ef10_rx_qstart;
static int
-sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
+sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr,
+ const efx_rx_prefix_layout_t *pinfo)
{
struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
SFC_ASSERT(rxq->pending == 0);
SFC_ASSERT(rxq->added == 0);
+ if (pinfo->erpl_length != rxq->prefix_size ||
+ efx_rx_prefix_layout_check(pinfo, &sfc_ef10_rx_prefix_layout) != 0)
+ return ENOTSUP;
+
sfc_ef10_rx_qrefill(rxq);
rxq->evq_read_ptr = evq_read_ptr;
},
.features = SFC_DP_RX_FEAT_MULTI_PROCESS |
SFC_DP_RX_FEAT_INTR,
- .dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM |
- DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
- DEV_RX_OFFLOAD_RSS_HASH,
- .queue_offload_capa = DEV_RX_OFFLOAD_SCATTER,
+ .dev_offload_capa = RTE_ETH_RX_OFFLOAD_CHECKSUM |
+ RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ RTE_ETH_RX_OFFLOAD_RSS_HASH,
+ .queue_offload_capa = RTE_ETH_RX_OFFLOAD_SCATTER,
.get_dev_info = sfc_ef10_rx_get_dev_info,
.qsize_up_rings = sfc_ef10_rx_qsize_up_rings,
.qcreate = sfc_ef10_rx_qcreate,