net/cnxk: support CPT CTX write through microcode op

[dpdk.git] / drivers / net / sfc / sfc_ef10_rx_ev.h

diff --git a/drivers/net/sfc/sfc_ef10_rx_ev.h b/drivers/net/sfc/sfc_ef10_rx_ev.h
index 868c755..821e222 100644 (file)
--- a/drivers/net/sfc/sfc_ef10_rx_ev.h
+++ b/drivers/net/sfc/sfc_ef10_rx_ev.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright (c) 2018 Solarflare Communications Inc.
- * All rights reserved.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
+ * Copyright(c) 2018-2019 Solarflare Communications Inc.
  *
  * This software was jointly developed between OKTET Labs (under contract
  * for Solarflare) and Solarflare Communications, Inc.
@@ -16,6 +16,8 @@
 #include "efx_regs.h"
 #include "efx_regs_ef10.h"
 
+#include "sfc_debug.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -25,9 +27,9 @@ sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
                           uint64_t ol_mask)
 {
        uint32_t tun_ptype = 0;
-       /* Which event bit is mapped to PKT_RX_IP_CKSUM_* */
+       /* Which event bit is mapped to RTE_MBUF_F_RX_IP_CKSUM_* */
        int8_t ip_csum_err_bit;
-       /* Which event bit is mapped to PKT_RX_L4_CKSUM_* */
+       /* Which event bit is mapped to RTE_MBUF_F_RX_L4_CKSUM_* */
        int8_t l4_csum_err_bit;
        uint32_t l2_ptype = 0;
        uint32_t l3_ptype = 0;
@@ -74,7 +76,7 @@ sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
                l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN;
                if (unlikely(EFX_TEST_QWORD_BIT(rx_ev,
                                                ESF_DZ_RX_IPCKSUM_ERR_LBN)))
-                       ol_flags |= PKT_RX_EIP_CKSUM_BAD;
+                       ol_flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
        }
 
        switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) {
@@ -103,9 +105,9 @@ sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
        case ESE_DZ_L3_CLASS_IP4:
                l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN :
                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
-               ol_flags |= PKT_RX_RSS_HASH |
+               ol_flags |= RTE_MBUF_F_RX_RSS_HASH |
                        ((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ?
-                        PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD);
+                        RTE_MBUF_F_RX_IP_CKSUM_BAD : RTE_MBUF_F_RX_IP_CKSUM_GOOD);
                break;
        case ESE_DZ_L3_CLASS_IP6_FRAG:
                l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
@@ -114,7 +116,7 @@ sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
        case ESE_DZ_L3_CLASS_IP6:
                l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
-               ol_flags |= PKT_RX_RSS_HASH;
+               ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
                break;
        case ESE_DZ_L3_CLASS_ARP:
                /* Override Layer 2 packet type */
@@ -142,7 +144,7 @@ sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
                        RTE_PTYPE_INNER_L4_TCP;
                ol_flags |=
                        (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
-                       PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
+                       RTE_MBUF_F_RX_L4_CKSUM_BAD : RTE_MBUF_F_RX_L4_CKSUM_GOOD;
                break;
        case ESE_FZ_L4_CLASS_UDP:
                 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);
@@ -150,7 +152,7 @@ sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
                        RTE_PTYPE_INNER_L4_UDP;
                ol_flags |=
                        (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
-                       PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
+                       RTE_MBUF_F_RX_L4_CKSUM_BAD : RTE_MBUF_F_RX_L4_CKSUM_GOOD;
                break;
        case ESE_FZ_L4_CLASS_UNKNOWN:
                 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=