/* Autonegotiation may be disabled */
dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_1000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_1G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_10000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_10G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_25000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_25G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_40000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_40G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_50000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_50G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_100000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_100G;
dev_info->max_rx_queues = sa->rxq_max;
}
/* Initialize to hardware limits */
- dev_info->rx_desc_lim.nb_max = EFX_RXQ_MAXNDESCS;
- dev_info->rx_desc_lim.nb_min = EFX_RXQ_MINNDESCS;
+ dev_info->rx_desc_lim.nb_max = sa->rxq_max_entries;
+ dev_info->rx_desc_lim.nb_min = sa->rxq_min_entries;
/* The RXQ hardware requires that the descriptor count is a power
* of 2, but rx_desc_lim cannot properly describe that constraint.
*/
- dev_info->rx_desc_lim.nb_align = EFX_RXQ_MINNDESCS;
+ dev_info->rx_desc_lim.nb_align = sa->rxq_min_entries;
/* Initialize to hardware limits */
dev_info->tx_desc_lim.nb_max = sa->txq_max_entries;
- dev_info->tx_desc_lim.nb_min = EFX_TXQ_MINNDESCS;
+ dev_info->tx_desc_lim.nb_min = sa->txq_min_entries;
/*
* The TXQ hardware requires that the descriptor count is a power
* of 2, but tx_desc_lim cannot properly describe that constraint
*/
- dev_info->tx_desc_lim.nb_align = EFX_TXQ_MINNDESCS;
+ dev_info->tx_desc_lim.nb_align = sa->txq_min_entries;
if (sap->dp_rx->get_dev_info != NULL)
sap->dp_rx->get_dev_info(dev_info);
sfc_dev_supported_ptypes_get(struct rte_eth_dev *dev)
{
const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev);
- struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
- const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
- uint32_t tunnel_encaps = encp->enc_tunnel_encapsulations_supported;
- return sap->dp_rx->supported_ptypes_get(tunnel_encaps);
+ return sap->dp_rx->supported_ptypes_get(sap->shared->tunnel_encaps);
}
static int
}
static const struct eth_dev_ops sfc_eth_dev_secondary_ops = {
+ .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get,
.rx_queue_count = sfc_rx_queue_count,
.rx_descriptor_done = sfc_rx_descriptor_done,
.rx_descriptor_status = sfc_rx_descriptor_status,