#include "sfc_repr.h"
#include "sfc_sw_stats.h"
#include "sfc_switch.h"
+#include "sfc_nic_dma.h"
#define SFC_XSTAT_ID_INVALID_VAL UINT64_MAX
#define SFC_XSTAT_ID_INVALID_NAME '\0'
struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
struct sfc_rss *rss = &sas->rss;
struct sfc_mae *mae = &sa->mae;
- uint64_t txq_offloads_def = 0;
sfc_log_init(sa, "entry");
dev_info->max_vfs = sa->sriov.num_vfs;
/* Autonegotiation may be disabled */
- dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
+ dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED;
if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX))
- dev_info->speed_capa |= ETH_LINK_SPEED_1G;
+ dev_info->speed_capa |= RTE_ETH_LINK_SPEED_1G;
if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX))
- dev_info->speed_capa |= ETH_LINK_SPEED_10G;
+ dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10G;
if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX))
- dev_info->speed_capa |= ETH_LINK_SPEED_25G;
+ dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G;
if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX))
- dev_info->speed_capa |= ETH_LINK_SPEED_40G;
+ dev_info->speed_capa |= RTE_ETH_LINK_SPEED_40G;
if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX))
- dev_info->speed_capa |= ETH_LINK_SPEED_50G;
+ dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G;
if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX))
- dev_info->speed_capa |= ETH_LINK_SPEED_100G;
+ dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G;
dev_info->max_rx_queues = sa->rxq_max;
dev_info->max_tx_queues = sa->txq_max;
dev_info->tx_offload_capa = sfc_tx_get_dev_offload_caps(sa) |
dev_info->tx_queue_offload_capa;
- if (dev_info->tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE)
- txq_offloads_def |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
-
- dev_info->default_txconf.offloads |= txq_offloads_def;
-
if (rss->context_type != EFX_RX_SCALE_UNAVAILABLE) {
uint64_t rte_hf = 0;
unsigned int i;
dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+ dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
- if (mae->status == SFC_MAE_STATUS_SUPPORTED) {
+ if (mae->status == SFC_MAE_STATUS_SUPPORTED ||
+ mae->status == SFC_MAE_STATUS_ADMIN) {
dev_info->switch_info.name = dev->device->driver->name;
dev_info->switch_info.domain_id = mae->switch_domain_id;
dev_info->switch_info.port_id = mae->switch_port_id;
sfc_eth_dev_clear_ops(dev);
+ sfc_nic_dma_detach(sa);
sfc_detach(sa);
sfc_unprobe(sa);
switch (link_fc) {
case 0:
- fc_conf->mode = RTE_FC_NONE;
+ fc_conf->mode = RTE_ETH_FC_NONE;
break;
case EFX_FCNTL_RESPOND:
- fc_conf->mode = RTE_FC_RX_PAUSE;
+ fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
break;
case EFX_FCNTL_GENERATE:
- fc_conf->mode = RTE_FC_TX_PAUSE;
+ fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
break;
case (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE):
- fc_conf->mode = RTE_FC_FULL;
+ fc_conf->mode = RTE_ETH_FC_FULL;
break;
default:
sfc_err(sa, "%s: unexpected flow control value %#x",
}
switch (fc_conf->mode) {
- case RTE_FC_NONE:
+ case RTE_ETH_FC_NONE:
fcntl = 0;
break;
- case RTE_FC_RX_PAUSE:
+ case RTE_ETH_FC_RX_PAUSE:
fcntl = EFX_FCNTL_RESPOND;
break;
- case RTE_FC_TX_PAUSE:
+ case RTE_ETH_FC_TX_PAUSE:
fcntl = EFX_FCNTL_GENERATE;
break;
- case RTE_FC_FULL:
+ case RTE_ETH_FC_FULL:
fcntl = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
break;
default:
qinfo->conf.rx_deferred_start = rxq_info->deferred_start;
qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
if (rxq_info->type_flags & EFX_RXQ_FLAG_SCATTER) {
- qinfo->conf.offloads |= DEV_RX_OFFLOAD_SCATTER;
+ qinfo->conf.offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
qinfo->scattered_rx = 1;
}
qinfo->nb_desc = rxq_info->entries;
sfc_tunnel_rte_type_to_efx_udp_proto(enum rte_eth_tunnel_type rte_type)
{
switch (rte_type) {
- case RTE_TUNNEL_TYPE_VXLAN:
+ case RTE_ETH_TUNNEL_TYPE_VXLAN:
return EFX_TUNNEL_PROTOCOL_VXLAN;
- case RTE_TUNNEL_TYPE_GENEVE:
+ case RTE_ETH_TUNNEL_TYPE_GENEVE:
return EFX_TUNNEL_PROTOCOL_GENEVE;
default:
return EFX_TUNNEL_NPROTOS;
/*
* Mapping of hash configuration between RTE and EFX is not one-to-one,
- * hence, conversion is done here to derive a correct set of ETH_RSS
+ * hence, conversion is done here to derive a correct set of RTE_ETH_RSS
* flags which corresponds to the active EFX configuration stored
* locally in 'sfc_adapter' and kept up-to-date
*/
struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
unsigned int efx_hash_types;
- uint32_t contexts[] = {EFX_RSS_CONTEXT_DEFAULT, rss->dummy_rss_context};
unsigned int n_contexts;
unsigned int mode_i = 0;
unsigned int key_i = 0;
+ uint32_t contexts[2];
unsigned int i = 0;
int rc = 0;
- n_contexts = rss->dummy_rss_context == EFX_RSS_CONTEXT_DEFAULT ? 1 : 2;
-
if (sfc_sa2shared(sa)->isolated)
return -ENOTSUP;
if (rc != 0)
goto fail_rx_hf_rte_to_efx;
+ contexts[0] = EFX_RSS_CONTEXT_DEFAULT;
+ contexts[1] = rss->dummy_ctx.nic_handle;
+ n_contexts = (rss->dummy_ctx.nic_handle_refcnt == 0) ? 1 : 2;
+
for (mode_i = 0; mode_i < n_contexts; mode_i++) {
rc = efx_rx_scale_mode_set(sa->nic, contexts[mode_i],
rss->hash_alg, efx_hash_types,
return -EINVAL;
for (entry = 0; entry < reta_size; entry++) {
- int grp = entry / RTE_RETA_GROUP_SIZE;
- int grp_idx = entry % RTE_RETA_GROUP_SIZE;
+ int grp = entry / RTE_ETH_RETA_GROUP_SIZE;
+ int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE;
if ((reta_conf[grp].mask >> grp_idx) & 1)
reta_conf[grp].reta[grp_idx] = rss->tbl[entry];
rte_memcpy(rss_tbl_new, rss->tbl, sizeof(rss->tbl));
for (entry = 0; entry < reta_size; entry++) {
- int grp_idx = entry % RTE_RETA_GROUP_SIZE;
+ int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE;
struct rte_eth_rss_reta_entry64 *grp;
- grp = &reta_conf[entry / RTE_RETA_GROUP_SIZE];
+ grp = &reta_conf[entry / RTE_ETH_RETA_GROUP_SIZE];
if (grp->mask & (1ull << grp_idx)) {
if (grp->reta[grp_idx] >= rss->channels) {
sfc_adapter_lock(sa);
- if (sa->mae.status != SFC_MAE_STATUS_SUPPORTED) {
+ if (sa->mae.status != SFC_MAE_STATUS_ADMIN) {
sfc_adapter_unlock(sa);
return -ENOTSUP;
}
if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_MARK) != 0)
supported |= RTE_ETH_RX_METADATA_USER_MARK;
- if (sfc_flow_tunnel_is_supported(sa))
+ if (sfc_ft_is_supported(sa))
supported |= RTE_ETH_RX_METADATA_TUNNEL_ID;
sa->negotiated_rx_metadata = supported & *features;
goto fail_kvargs;
if (switch_mode == NULL) {
- sa->switchdev = encp->enc_mae_supported &&
+ sa->switchdev = encp->enc_mae_admin &&
(!encp->enc_datapath_cap_evb ||
has_representors);
} else if (strcasecmp(switch_mode, SFC_KVARG_SWITCH_MODE_LEGACY) == 0) {
if (rc != 0)
goto fail_attach;
- if (sa->switchdev && sa->mae.status != SFC_MAE_STATUS_SUPPORTED) {
+ if (sa->switchdev && sa->mae.status != SFC_MAE_STATUS_ADMIN) {
sfc_err(sa,
- "failed to enable switchdev mode without MAE support");
+ "failed to enable switchdev mode without admin MAE privilege");
rc = ENOTSUP;
goto fail_switchdev_no_mae;
}
from = (const struct rte_ether_addr *)(encp->enc_mac_addr);
rte_ether_addr_copy(from, &dev->data->mac_addrs[0]);
+ /*
+ * Setup the NIC DMA mapping handler. All internal mempools
+ * MUST be created on attach before this point, and the
+ * adapter MUST NOT create mempools with the adapter lock
+ * held after this point.
+ */
+ rc = sfc_nic_dma_attach(sa);
+ if (rc != 0)
+ goto fail_nic_dma_attach;
+
sfc_adapter_unlock(sa);
sfc_log_init(sa, "done");
return 0;
+fail_nic_dma_attach:
fail_switchdev_no_mae:
sfc_detach(sa);
{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) },
{ RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) },
{ RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) },
+ { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) },
{ .vendor_id = 0 /* sentinel */ }
};
git.droids-corp.org / dpdk.git / blobdiff