/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
* Copyright(c) 2016-2019 Solarflare Communications Inc.
*
* This software was jointly developed between OKTET Labs (under contract
*/
#include <rte_dev.h>
-#include <rte_ethdev_driver.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_driver.h>
+#include <ethdev_pci.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_errno.h>
struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev);
struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
struct sfc_rss *rss = &sas->rss;
+ struct sfc_mae *mae = &sa->mae;
uint64_t txq_offloads_def = 0;
sfc_log_init(sa, "entry");
dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+ if (mae->status == SFC_MAE_STATUS_SUPPORTED) {
+ dev_info->switch_info.name = dev->device->driver->name;
+ dev_info->switch_info.domain_id = mae->switch_domain_id;
+ dev_info->switch_info.port_id = mae->switch_port_id;
+ }
+
return 0;
}
return ret;
}
-static void
+static int
sfc_dev_stop(struct rte_eth_dev *dev)
{
struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
sfc_adapter_unlock(sa);
sfc_log_init(sa, "done");
+
+ return 0;
}
static int
sfc_eth_dev_secondary_clear_ops(struct rte_eth_dev *dev)
{
free(dev->process_private);
- dev->process_private = NULL;
- dev->dev_ops = NULL;
- dev->tx_pkt_prepare = NULL;
- dev->tx_pkt_burst = NULL;
- dev->rx_pkt_burst = NULL;
+ rte_eth_dev_release_port(dev);
}
static int
/* Required for logging, so cleanup last */
sa->eth_dev = NULL;
- dev->process_private = NULL;
free(sa);
return 0;
mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES];
stats->imissed = mac_stats[EFX_MAC_VADAPTER_RX_BAD_PACKETS];
stats->oerrors = mac_stats[EFX_MAC_VADAPTER_TX_BAD_PACKETS];
+
+ /* CRC is included in these stats, but shouldn't be */
+ stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;
+ stats->obytes -= stats->opackets * RTE_ETHER_CRC_LEN;
} else {
stats->opackets = mac_stats[EFX_MAC_TX_PKTS];
stats->ibytes = mac_stats[EFX_MAC_RX_OCTETS];
stats->obytes = mac_stats[EFX_MAC_TX_OCTETS];
+
+ /* CRC is included in these stats, but shouldn't be */
+ stats->ibytes -= mac_stats[EFX_MAC_RX_PKTS] * RTE_ETHER_CRC_LEN;
+ stats->obytes -= mac_stats[EFX_MAC_TX_PKTS] * RTE_ETHER_CRC_LEN;
+
/*
* Take into account stats which are whenever supported
* on EF10. If some stat is not supported by current
* The driver does not use it, but other PMDs update jumbo frame
* flag and max_rx_pkt_len when MTU is set.
*/
- if (mtu > RTE_ETHER_MAX_LEN) {
+ if (mtu > RTE_ETHER_MTU) {
struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
}
}
static int
-sfc_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type filter_type,
- enum rte_filter_op filter_op,
- void *arg)
+sfc_dev_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
+ const struct rte_flow_ops **ops)
{
- struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
- int rc = ENOTSUP;
-
- sfc_log_init(sa, "entry");
-
- switch (filter_type) {
- case RTE_ETH_FILTER_NONE:
- sfc_err(sa, "Global filters configuration not supported");
- break;
- case RTE_ETH_FILTER_MACVLAN:
- sfc_err(sa, "MACVLAN filters not supported");
- break;
- case RTE_ETH_FILTER_ETHERTYPE:
- sfc_err(sa, "EtherType filters not supported");
- break;
- case RTE_ETH_FILTER_FLEXIBLE:
- sfc_err(sa, "Flexible filters not supported");
- break;
- case RTE_ETH_FILTER_SYN:
- sfc_err(sa, "SYN filters not supported");
- break;
- case RTE_ETH_FILTER_NTUPLE:
- sfc_err(sa, "NTUPLE filters not supported");
- break;
- case RTE_ETH_FILTER_TUNNEL:
- sfc_err(sa, "Tunnel filters not supported");
- break;
- case RTE_ETH_FILTER_FDIR:
- sfc_err(sa, "Flow Director filters not supported");
- break;
- case RTE_ETH_FILTER_HASH:
- sfc_err(sa, "Hash filters not supported");
- break;
- case RTE_ETH_FILTER_GENERIC:
- if (filter_op != RTE_ETH_FILTER_GET) {
- rc = EINVAL;
- } else {
- *(const void **)arg = &sfc_flow_ops;
- rc = 0;
- }
- break;
- default:
- sfc_err(sa, "Unknown filter type %u", filter_type);
- break;
- }
-
- sfc_log_init(sa, "exit: %d", -rc);
- SFC_ASSERT(rc >= 0);
- return -rc;
+ *ops = &sfc_flow_ops;
+ return 0;
}
static int
.reta_query = sfc_dev_rss_reta_query,
.rss_hash_update = sfc_dev_rss_hash_update,
.rss_hash_conf_get = sfc_dev_rss_hash_conf_get,
- .filter_ctrl = sfc_dev_filter_ctrl,
+ .flow_ops_get = sfc_dev_flow_ops_get,
.set_mc_addr_list = sfc_set_mc_addr_list,
.rxq_info_get = sfc_rx_queue_info_get,
.txq_info_get = sfc_tx_queue_info_get,
sfc_dp_register(&sfc_dp_head, &sfc_ef10_rx.dp);
sfc_dp_register(&sfc_dp_head, &sfc_efx_rx.dp);
+ sfc_dp_register(&sfc_dp_head, &sfc_ef100_tx.dp);
sfc_dp_register(&sfc_dp_head, &sfc_ef10_tx.dp);
sfc_dp_register(&sfc_dp_head, &sfc_efx_tx.dp);
sfc_dp_register(&sfc_dp_head, &sfc_ef10_simple_tx.dp);
const struct rte_ether_addr *from;
int ret;
+ if (sfc_efx_dev_class_get(pci_dev->device.devargs) !=
+ SFC_EFX_DEV_CLASS_NET) {
+ SFC_GENERIC_LOG(DEBUG,
+ "Incompatible device class: skip probing, should be probed by other sfc driver.");
+ return 1;
+ }
+
sfc_register_dp();
logtype_main = sfc_register_logtype(&pci_dev->addr,
/* Copy PCI device info to the dev->data */
rte_eth_copy_pci_info(dev, pci_dev);
+ dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
+ dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
rc = sfc_kvargs_parse(sa);
if (rc != 0)