net/ionic: preserve Rx mode across LIF stop/start

[dpdk.git] / drivers / net / sfc / sfc_ethdev.c

diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index ca1b99a..93fc7ba 100644 (file)
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -93,6 +93,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev);
        struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
        struct sfc_rss *rss = &sas->rss;
+       struct sfc_mae *mae = &sa->mae;
        uint64_t txq_offloads_def = 0;
 
        sfc_log_init(sa, "entry");
@@ -187,6 +188,12 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                             RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 
+       if (mae->status == SFC_MAE_STATUS_SUPPORTED) {
+               dev_info->switch_info.name = dev->device->driver->name;
+               dev_info->switch_info.domain_id = mae->switch_domain_id;
+               dev_info->switch_info.port_id = mae->switch_port_id;
+       }
+
        return 0;
 }
 
@@ -276,7 +283,7 @@ sfc_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
        return ret;
 }
 
-static void
+static int
 sfc_dev_stop(struct rte_eth_dev *dev)
 {
        struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);
@@ -288,6 +295,8 @@ sfc_dev_stop(struct rte_eth_dev *dev)
        sfc_adapter_unlock(sa);
 
        sfc_log_init(sa, "done");
+
+       return 0;
 }
 
 static int
@@ -324,11 +333,7 @@ static void
 sfc_eth_dev_secondary_clear_ops(struct rte_eth_dev *dev)
 {
        free(dev->process_private);
-       dev->process_private = NULL;
-       dev->dev_ops = NULL;
-       dev->tx_pkt_prepare = NULL;
-       dev->tx_pkt_burst = NULL;
-       dev->rx_pkt_burst = NULL;
+       rte_eth_dev_release_port(dev);
 }
 
 static int
@@ -380,7 +385,6 @@ sfc_dev_close(struct rte_eth_dev *dev)
        /* Required for logging, so cleanup last */
        sa->eth_dev = NULL;
 
-       dev->process_private = NULL;
        free(sa);
 
        return 0;
@@ -1748,33 +1752,6 @@ sfc_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type filter_type,
        sfc_log_init(sa, "entry");
 
        switch (filter_type) {
-       case RTE_ETH_FILTER_NONE:
-               sfc_err(sa, "Global filters configuration not supported");
-               break;
-       case RTE_ETH_FILTER_MACVLAN:
-               sfc_err(sa, "MACVLAN filters not supported");
-               break;
-       case RTE_ETH_FILTER_ETHERTYPE:
-               sfc_err(sa, "EtherType filters not supported");
-               break;
-       case RTE_ETH_FILTER_FLEXIBLE:
-               sfc_err(sa, "Flexible filters not supported");
-               break;
-       case RTE_ETH_FILTER_SYN:
-               sfc_err(sa, "SYN filters not supported");
-               break;
-       case RTE_ETH_FILTER_NTUPLE:
-               sfc_err(sa, "NTUPLE filters not supported");
-               break;
-       case RTE_ETH_FILTER_TUNNEL:
-               sfc_err(sa, "Tunnel filters not supported");
-               break;
-       case RTE_ETH_FILTER_FDIR:
-               sfc_err(sa, "Flow Director filters not supported");
-               break;
-       case RTE_ETH_FILTER_HASH:
-               sfc_err(sa, "Hash filters not supported");
-               break;
        case RTE_ETH_FILTER_GENERIC:
                if (filter_op != RTE_ETH_FILTER_GET) {
                        rc = EINVAL;
@@ -1924,6 +1901,11 @@ sfc_eth_dev_set_ops(struct rte_eth_dev *dev)
        case EFX_FAMILY_MEDFORD:
        case EFX_FAMILY_MEDFORD2:
                avail_caps |= SFC_DP_HW_FW_CAP_EF10;
+               avail_caps |= SFC_DP_HW_FW_CAP_RX_EFX;
+               avail_caps |= SFC_DP_HW_FW_CAP_TX_EFX;
+               break;
+       case EFX_FAMILY_RIVERHEAD:
+               avail_caps |= SFC_DP_HW_FW_CAP_EF100;
                break;
        default:
                break;
@@ -2146,10 +2128,12 @@ sfc_register_dp(void)
        /* Register once */
        if (TAILQ_EMPTY(&sfc_dp_head)) {
                /* Prefer EF10 datapath */
+               sfc_dp_register(&sfc_dp_head, &sfc_ef100_rx.dp);
                sfc_dp_register(&sfc_dp_head, &sfc_ef10_essb_rx.dp);
                sfc_dp_register(&sfc_dp_head, &sfc_ef10_rx.dp);
                sfc_dp_register(&sfc_dp_head, &sfc_efx_rx.dp);
 
+               sfc_dp_register(&sfc_dp_head, &sfc_ef100_tx.dp);
                sfc_dp_register(&sfc_dp_head, &sfc_ef10_tx.dp);
                sfc_dp_register(&sfc_dp_head, &sfc_efx_tx.dp);
                sfc_dp_register(&sfc_dp_head, &sfc_ef10_simple_tx.dp);
@@ -2213,6 +2197,8 @@ sfc_eth_dev_init(struct rte_eth_dev *dev)
 
        /* Copy PCI device info to the dev->data */
        rte_eth_copy_pci_info(dev, pci_dev);
+       dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
+       dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
 
        rc = sfc_kvargs_parse(sa);
        if (rc != 0)
@@ -2300,6 +2286,7 @@ static const struct rte_pci_id pci_id_sfc_efx_map[] = {
        { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD_VF) },
        { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) },
        { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) },
+       { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) },
        { .vendor_id = 0 /* sentinel */ }
 };