net/avf: fix Tx offload mask

[dpdk.git] / drivers / net / softnic / rte_eth_softnic_thread.c

diff --git a/drivers/net/softnic/rte_eth_softnic_thread.c b/drivers/net/softnic/rte_eth_softnic_thread.c
index 11d08d4..4572adf 100644 (file)
--- a/drivers/net/softnic/rte_eth_softnic_thread.c
+++ b/drivers/net/softnic/rte_eth_softnic_thread.c
@@ -1902,6 +1902,11 @@ softnic_pipeline_table_dscp_table_update(struct pmd_internals *softnic,
                                dscp_mask,
                                dscp_table);
 
+               /* Update table dscp table */
+               if (!status)
+                       memcpy(&p->table[table_id].dscp_table, dscp_table,
+                               sizeof(p->table[table_id].dscp_table));
+
                return status;
        }
 
@@ -1925,6 +1930,11 @@ softnic_pipeline_table_dscp_table_update(struct pmd_internals *softnic,
        /* Read response */
        status = rsp->status;
 
+       /* Update table dscp table */
+       if (!status)
+               memcpy(&p->table[table_id].dscp_table, dscp_table,
+                       sizeof(p->table[table_id].dscp_table));
+
        /* Free response */
        pipeline_msg_free(rsp);
 
@@ -2230,29 +2240,37 @@ match_convert(struct softnic_table_rule_match *mh,
                                ml->acl_add.field_value[0].mask_range.u8 =
                                        mh->match.acl.proto_mask;
 
-                               ml->acl_add.field_value[1].value.u32 = sa32[0];
+                               ml->acl_add.field_value[1].value.u32 =
+                                       rte_be_to_cpu_32(sa32[0]);
                                ml->acl_add.field_value[1].mask_range.u32 =
                                        sa32_depth[0];
-                               ml->acl_add.field_value[2].value.u32 = sa32[1];
+                               ml->acl_add.field_value[2].value.u32 =
+                                       rte_be_to_cpu_32(sa32[1]);
                                ml->acl_add.field_value[2].mask_range.u32 =
                                        sa32_depth[1];
-                               ml->acl_add.field_value[3].value.u32 = sa32[2];
+                               ml->acl_add.field_value[3].value.u32 =
+                                       rte_be_to_cpu_32(sa32[2]);
                                ml->acl_add.field_value[3].mask_range.u32 =
                                        sa32_depth[2];
-                               ml->acl_add.field_value[4].value.u32 = sa32[3];
+                               ml->acl_add.field_value[4].value.u32 =
+                                       rte_be_to_cpu_32(sa32[3]);
                                ml->acl_add.field_value[4].mask_range.u32 =
                                        sa32_depth[3];
 
-                               ml->acl_add.field_value[5].value.u32 = da32[0];
+                               ml->acl_add.field_value[5].value.u32 =
+                                       rte_be_to_cpu_32(da32[0]);
                                ml->acl_add.field_value[5].mask_range.u32 =
                                        da32_depth[0];
-                               ml->acl_add.field_value[6].value.u32 = da32[1];
+                               ml->acl_add.field_value[6].value.u32 =
+                                       rte_be_to_cpu_32(da32[1]);
                                ml->acl_add.field_value[6].mask_range.u32 =
                                        da32_depth[1];
-                               ml->acl_add.field_value[7].value.u32 = da32[2];
+                               ml->acl_add.field_value[7].value.u32 =
+                                       rte_be_to_cpu_32(da32[2]);
                                ml->acl_add.field_value[7].mask_range.u32 =
                                        da32_depth[2];
-                               ml->acl_add.field_value[8].value.u32 = da32[3];
+                               ml->acl_add.field_value[8].value.u32 =
+                                       rte_be_to_cpu_32(da32[3]);
                                ml->acl_add.field_value[8].mask_range.u32 =
                                        da32_depth[3];
 
@@ -2292,36 +2310,36 @@ match_convert(struct softnic_table_rule_match *mh,
                                        mh->match.acl.proto_mask;
 
                                ml->acl_delete.field_value[1].value.u32 =
-                                       sa32[0];
+                                       rte_be_to_cpu_32(sa32[0]);
                                ml->acl_delete.field_value[1].mask_range.u32 =
                                        sa32_depth[0];
                                ml->acl_delete.field_value[2].value.u32 =
-                                       sa32[1];
+                                       rte_be_to_cpu_32(sa32[1]);
                                ml->acl_delete.field_value[2].mask_range.u32 =
                                        sa32_depth[1];
                                ml->acl_delete.field_value[3].value.u32 =
-                                       sa32[2];
+                                       rte_be_to_cpu_32(sa32[2]);
                                ml->acl_delete.field_value[3].mask_range.u32 =
                                        sa32_depth[2];
                                ml->acl_delete.field_value[4].value.u32 =
-                                       sa32[3];
+                                       rte_be_to_cpu_32(sa32[3]);
                                ml->acl_delete.field_value[4].mask_range.u32 =
                                        sa32_depth[3];
 
                                ml->acl_delete.field_value[5].value.u32 =
-                                       da32[0];
+                                       rte_be_to_cpu_32(da32[0]);
                                ml->acl_delete.field_value[5].mask_range.u32 =
                                        da32_depth[0];
                                ml->acl_delete.field_value[6].value.u32 =
-                                       da32[1];
+                                       rte_be_to_cpu_32(da32[1]);
                                ml->acl_delete.field_value[6].mask_range.u32 =
                                        da32_depth[1];
                                ml->acl_delete.field_value[7].value.u32 =
-                                       da32[2];
+                                       rte_be_to_cpu_32(da32[2]);
                                ml->acl_delete.field_value[7].mask_range.u32 =
                                        da32_depth[2];
                                ml->acl_delete.field_value[8].value.u32 =
-                                       da32[3];
+                                       rte_be_to_cpu_32(da32[3]);
                                ml->acl_delete.field_value[8].mask_range.u32 =
                                        da32_depth[3];
 
@@ -2460,6 +2478,36 @@ action_convert(struct rte_table_action *a,
                        return status;
        }
 
+       if (action->action_mask & (1LLU << RTE_TABLE_ACTION_TAG)) {
+               status = rte_table_action_apply(a,
+                       data,
+                       RTE_TABLE_ACTION_TAG,
+                       &action->tag);
+
+               if (status)
+                       return status;
+       }
+
+       if (action->action_mask & (1LLU << RTE_TABLE_ACTION_DECAP)) {
+               status = rte_table_action_apply(a,
+                       data,
+                       RTE_TABLE_ACTION_DECAP,
+                       &action->decap);
+
+               if (status)
+                       return status;
+       }
+
+       if (action->action_mask & (1LLU << RTE_TABLE_ACTION_SYM_CRYPTO)) {
+               status = rte_table_action_apply(a,
+                       data,
+                       RTE_TABLE_ACTION_SYM_CRYPTO,
+                       &action->sym_crypto);
+
+               if (status)
+                       return status;
+       }
+
        return 0;
 }