update Cavium Inc copyright headers
[dpdk.git] / drivers / net / thunderx / base / nicvf_hw.c
index ec24f9c..c9f0d26 100644 (file)
@@ -1,7 +1,7 @@
 /*
  *   BSD LICENSE
  *
- *   Copyright (C) Cavium networks Ltd. 2016.
+ *   Copyright (C) Cavium, Inc. 2016.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
@@ -13,7 +13,7 @@
  *       notice, this list of conditions and the following disclaimer in
  *       the documentation and/or other materials provided with the
  *       distribution.
- *     * Neither the name of Cavium networks nor the names of its
+ *     * Neither the name of Cavium, Inc nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
@@ -140,8 +140,15 @@ nicvf_base_init(struct nicvf *nic)
        if (nic->subsystem_device_id == 0)
                return NICVF_ERR_BASE_INIT;
 
-       if (nicvf_hw_version(nic) == NICVF_PASS2)
-               nic->hwcap |= NICVF_CAP_TUNNEL_PARSING;
+       if (nicvf_hw_version(nic) == PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF)
+               nic->hwcap |= NICVF_CAP_TUNNEL_PARSING | NICVF_CAP_CQE_RX2;
+
+       if (nicvf_hw_version(nic) == PCI_SUB_DEVICE_ID_CN81XX_NICVF)
+               nic->hwcap |= NICVF_CAP_TUNNEL_PARSING | NICVF_CAP_CQE_RX2;
+
+       if (nicvf_hw_version(nic) == PCI_SUB_DEVICE_ID_CN83XX_NICVF)
+               nic->hwcap |= NICVF_CAP_TUNNEL_PARSING | NICVF_CAP_CQE_RX2 |
+                               NICVF_CAP_DISABLE_APAD;
 
        return NICVF_OK;
 }
@@ -494,9 +501,9 @@ nicvf_qsize_rbdr_roundup(uint32_t val)
 }
 
 int
-nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
-                         rbdr_pool_get_handler handler,
-                         void *opaque, uint32_t max_buffs)
+nicvf_qset_rbdr_precharge(void *dev, struct nicvf *nic,
+                         uint16_t ridx, rbdr_pool_get_handler handler,
+                         uint32_t max_buffs)
 {
        struct rbdr_entry_t *desc, *desc0;
        struct nicvf_rbdr *rbdr = nic->rbdr;
@@ -511,7 +518,7 @@ nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
                if (count >= max_buffs)
                        break;
                desc0 = desc + count;
-               phy = handler(opaque);
+               phy = handler(dev, nic);
                if (phy) {
                        desc0->full_addr = phy;
                        count++;
@@ -721,6 +728,153 @@ nicvf_vlan_hw_strip(struct nicvf *nic, bool enable)
        nicvf_reg_write(nic, NIC_VNIC_RQ_GEN_CFG, val);
 }
 
+void
+nicvf_apad_config(struct nicvf *nic, bool enable)
+{
+       uint64_t val;
+
+       /* APAD always enabled in this device */
+       if (!(nic->hwcap & NICVF_CAP_DISABLE_APAD))
+               return;
+
+       val = nicvf_reg_read(nic, NIC_VNIC_RQ_GEN_CFG);
+       if (enable)
+               val &= ~(1ULL << NICVF_QS_RQ_DIS_APAD_SHIFT);
+       else
+               val |= (1ULL << NICVF_QS_RQ_DIS_APAD_SHIFT);
+
+       nicvf_reg_write(nic, NIC_VNIC_RQ_GEN_CFG, val);
+}
+
+void
+nicvf_rss_set_key(struct nicvf *nic, uint8_t *key)
+{
+       int idx;
+       uint64_t addr, val;
+       uint64_t *keyptr = (uint64_t *)key;
+
+       addr = NIC_VNIC_RSS_KEY_0_4;
+       for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
+               val = nicvf_cpu_to_be_64(*keyptr);
+               nicvf_reg_write(nic, addr, val);
+               addr += sizeof(uint64_t);
+               keyptr++;
+       }
+}
+
+void
+nicvf_rss_get_key(struct nicvf *nic, uint8_t *key)
+{
+       int idx;
+       uint64_t addr, val;
+       uint64_t *keyptr = (uint64_t *)key;
+
+       addr = NIC_VNIC_RSS_KEY_0_4;
+       for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
+               val = nicvf_reg_read(nic, addr);
+               *keyptr = nicvf_be_to_cpu_64(val);
+               addr += sizeof(uint64_t);
+               keyptr++;
+       }
+}
+
+void
+nicvf_rss_set_cfg(struct nicvf *nic, uint64_t val)
+{
+       nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, val);
+}
+
+uint64_t
+nicvf_rss_get_cfg(struct nicvf *nic)
+{
+       return nicvf_reg_read(nic, NIC_VNIC_RSS_CFG);
+}
+
+int
+nicvf_rss_reta_update(struct nicvf *nic, uint8_t *tbl, uint32_t max_count)
+{
+       uint32_t idx;
+       struct nicvf_rss_reta_info *rss = &nic->rss_info;
+
+       /* result will be stored in nic->rss_info.rss_size */
+       if (nicvf_mbox_get_rss_size(nic))
+               return NICVF_ERR_RSS_GET_SZ;
+
+       assert(rss->rss_size > 0);
+       rss->hash_bits = (uint8_t)log2(rss->rss_size);
+       for (idx = 0; idx < rss->rss_size && idx < max_count; idx++)
+               rss->ind_tbl[idx] = tbl[idx];
+
+       if (nicvf_mbox_config_rss(nic))
+               return NICVF_ERR_RSS_TBL_UPDATE;
+
+       return NICVF_OK;
+}
+
+int
+nicvf_rss_reta_query(struct nicvf *nic, uint8_t *tbl, uint32_t max_count)
+{
+       uint32_t idx;
+       struct nicvf_rss_reta_info *rss = &nic->rss_info;
+
+       /* result will be stored in nic->rss_info.rss_size */
+       if (nicvf_mbox_get_rss_size(nic))
+               return NICVF_ERR_RSS_GET_SZ;
+
+       assert(rss->rss_size > 0);
+       rss->hash_bits = (uint8_t)log2(rss->rss_size);
+       for (idx = 0; idx < rss->rss_size && idx < max_count; idx++)
+               tbl[idx] = rss->ind_tbl[idx];
+
+       return NICVF_OK;
+}
+
+int
+nicvf_rss_config(struct nicvf *nic, uint32_t  qcnt, uint64_t cfg)
+{
+       uint32_t idx;
+       uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
+       uint8_t default_key[RSS_HASH_KEY_BYTE_SIZE] = {
+               0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
+               0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
+               0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
+               0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
+               0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD
+       };
+
+       if (nic->cpi_alg != CPI_ALG_NONE)
+               return -EINVAL;
+
+       if (cfg == 0)
+               return -EINVAL;
+
+       /* Update default RSS key and cfg */
+       nicvf_rss_set_key(nic, default_key);
+       nicvf_rss_set_cfg(nic, cfg);
+
+       /* Update default RSS RETA */
+       for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
+               default_reta[idx] = idx % qcnt;
+
+       return nicvf_rss_reta_update(nic, default_reta,
+                       NIC_MAX_RSS_IDR_TBL_SIZE);
+}
+
+int
+nicvf_rss_term(struct nicvf *nic)
+{
+       uint32_t idx;
+       uint8_t disable_rss[NIC_MAX_RSS_IDR_TBL_SIZE];
+
+       nicvf_rss_set_cfg(nic, 0);
+       /* Redirect the output to 0th queue  */
+       for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
+               disable_rss[idx] = 0;
+
+       return nicvf_rss_reta_update(nic, disable_rss,
+                       NIC_MAX_RSS_IDR_TBL_SIZE);
+}
+
 int
 nicvf_loopback_config(struct nicvf *nic, bool enable)
 {
@@ -729,3 +883,48 @@ nicvf_loopback_config(struct nicvf *nic, bool enable)
 
        return nicvf_mbox_loopback_config(nic, enable);
 }
+
+void
+nicvf_hw_get_stats(struct nicvf *nic, struct nicvf_hw_stats *stats)
+{
+       stats->rx_bytes = NICVF_GET_RX_STATS(RX_OCTS);
+       stats->rx_ucast_frames = NICVF_GET_RX_STATS(RX_UCAST);
+       stats->rx_bcast_frames = NICVF_GET_RX_STATS(RX_BCAST);
+       stats->rx_mcast_frames = NICVF_GET_RX_STATS(RX_MCAST);
+       stats->rx_fcs_errors = NICVF_GET_RX_STATS(RX_FCS);
+       stats->rx_l2_errors = NICVF_GET_RX_STATS(RX_L2ERR);
+       stats->rx_drop_red = NICVF_GET_RX_STATS(RX_RED);
+       stats->rx_drop_red_bytes = NICVF_GET_RX_STATS(RX_RED_OCTS);
+       stats->rx_drop_overrun = NICVF_GET_RX_STATS(RX_ORUN);
+       stats->rx_drop_overrun_bytes = NICVF_GET_RX_STATS(RX_ORUN_OCTS);
+       stats->rx_drop_bcast = NICVF_GET_RX_STATS(RX_DRP_BCAST);
+       stats->rx_drop_mcast = NICVF_GET_RX_STATS(RX_DRP_MCAST);
+       stats->rx_drop_l3_bcast = NICVF_GET_RX_STATS(RX_DRP_L3BCAST);
+       stats->rx_drop_l3_mcast = NICVF_GET_RX_STATS(RX_DRP_L3MCAST);
+
+       stats->tx_bytes_ok = NICVF_GET_TX_STATS(TX_OCTS);
+       stats->tx_ucast_frames_ok = NICVF_GET_TX_STATS(TX_UCAST);
+       stats->tx_bcast_frames_ok = NICVF_GET_TX_STATS(TX_BCAST);
+       stats->tx_mcast_frames_ok = NICVF_GET_TX_STATS(TX_MCAST);
+       stats->tx_drops = NICVF_GET_TX_STATS(TX_DROP);
+}
+
+void
+nicvf_hw_get_rx_qstats(struct nicvf *nic, struct nicvf_hw_rx_qstats *qstats,
+                      uint16_t qidx)
+{
+       qstats->q_rx_bytes =
+               nicvf_queue_reg_read(nic, NIC_QSET_RQ_0_7_STATUS0, qidx);
+       qstats->q_rx_packets =
+               nicvf_queue_reg_read(nic, NIC_QSET_RQ_0_7_STATUS1, qidx);
+}
+
+void
+nicvf_hw_get_tx_qstats(struct nicvf *nic, struct nicvf_hw_tx_qstats *qstats,
+                      uint16_t qidx)
+{
+       qstats->q_tx_bytes =
+               nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_STATUS0, qidx);
+       qstats->q_tx_packets =
+               nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_STATUS1, qidx);
+}