#define PCI_DEVICE_ID_THUNDERX_NICVF 0xA034
#define PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF 0xA11E
#define PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF 0xA134
+#define PCI_SUB_DEVICE_ID_CN81XX_NICVF 0xA234
#define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define NICVF_GET_TX_STATS(reg) \
nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
-
-#define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
+#define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
+/* Additional word in Rx descriptor to hold optional tunneling extension info */
+#define NICVF_CAP_CQE_RX2 (1ULL << 1)
enum nicvf_tns_mode {
NIC_TNS_BYPASS_MODE,
NICVF_ERR_RSS_GET_SZ, /* -8171 */
};
-typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *opaque);
+typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *dev, void *opaque);
struct nicvf_hw_rx_qstats {
uint64_t q_rx_bytes;
int nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx);
int nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx);
-int nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
- rbdr_pool_get_handler handler, void *opaque,
+int nicvf_qset_rbdr_precharge(void *dev, struct nicvf *nic,
+ uint16_t ridx, rbdr_pool_get_handler handler,
uint32_t max_buffs);
int nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx);