net/ice: support L4 for QinQ switch filter

[dpdk.git] / drivers / net / txgbe / base / txgbe_phy.c

diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 5402a06..2db87ae 100644 (file)
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015-2020
+ * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
  */
 
 #include "txgbe_hw.h"
@@ -7,7 +8,7 @@
 #include "txgbe_mng.h"
 #include "txgbe_phy.h"
 
-static void txgbe_i2c_start(struct txgbe_hw *hw);
+static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr);
 static void txgbe_i2c_stop(struct txgbe_hw *hw);
 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw);
 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
@@ -1247,11 +1248,9 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
                                           u8 dev_addr, u8 *data)
 {
-       UNREFERENCED_PARAMETER(dev_addr);
-
        DEBUGFUNC("txgbe_read_i2c_byte");
 
-       txgbe_i2c_start(hw);
+       txgbe_i2c_start(hw, dev_addr);
 
        /* wait tx empty */
        if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
@@ -1313,11 +1312,9 @@ s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
                                            u8 dev_addr, u8 data)
 {
-       UNREFERENCED_PARAMETER(dev_addr);
-
        DEBUGFUNC("txgbe_write_i2c_byte");
 
-       txgbe_i2c_start(hw);
+       txgbe_i2c_start(hw, dev_addr);
 
        /* wait tx empty */
        if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
@@ -1368,7 +1365,7 @@ s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
  *
  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
  **/
-static void txgbe_i2c_start(struct txgbe_hw *hw)
+static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr)
 {
        DEBUGFUNC("txgbe_i2c_start");
 
@@ -1379,9 +1376,9 @@ static void txgbe_i2c_start(struct txgbe_hw *hw)
                TXGBE_I2CCON_SPEED(1) |
                TXGBE_I2CCON_RESTART |
                TXGBE_I2CCON_SDIA));
-       wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR);
-       wr32(hw, TXGBE_I2CSSSCLHCNT, 600);
-       wr32(hw, TXGBE_I2CSSSCLLCNT, 600);
+       wr32(hw, TXGBE_I2CTAR, dev_addr >> 1);
+       wr32(hw, TXGBE_I2CSSSCLHCNT, 200);
+       wr32(hw, TXGBE_I2CSSSCLLCNT, 200);
        wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
        wr32(hw, TXGBE_I2CTXTL, 4);
        wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
@@ -1513,6 +1510,15 @@ txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
        } else {
                wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);
        }
+
+       if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
+               value = (0x1804 & ~0x3F3F);
+               value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+               value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+       }
 out:
        return err;
 }
@@ -1710,7 +1716,14 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
                goto out;
        }
 
-       if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+       if (hw->phy.ffe_set == TXGBE_BP_M_KX4) {
+               value = (0x1804 & ~0x3F3F);
+               value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+               value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+       } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
                value = (0x1804 & ~0x3F3F);
                wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
 
@@ -1917,7 +1930,15 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
                goto out;
        }
 
-       if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+       if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
+               value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
+               value |= hw->phy.ffe_post | (1 << 6);
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+       } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
                value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
                wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
 
@@ -2144,7 +2165,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,
                goto out;
        }
 
-       if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+       if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
+               value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
+               value |= hw->phy.ffe_post | (1 << 6);
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+       } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
                value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
                value = (value & ~0x3F3F) | (24 << 8) | 4;
                wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
@@ -2318,6 +2347,66 @@ void txgbe_bp_down_event(struct txgbe_hw *hw)
        txgbe_set_link_to_kr(hw, 0);
 }
 
+void txgbe_bp_mode_set(struct txgbe_hw *hw)
+{
+       if (hw->phy.ffe_set == TXGBE_BP_M_SFI)
+               hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP;
+       else if (hw->phy.ffe_set == TXGBE_BP_M_KR)
+               hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4;
+       else if (hw->phy.ffe_set == TXGBE_BP_M_KX4)
+               hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI;
+       else if (hw->phy.ffe_set == TXGBE_BP_M_KX)
+               hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII;
+}
+
+void txgbe_set_phy_temp(struct txgbe_hw *hw)
+{
+       u32 value;
+
+       if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
+               BP_LOG("Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\n",
+                       hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
+
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
+               value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
+                       hw->phy.ffe_pre;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
+               value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+       }
+
+       if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
+               BP_LOG("Set KR TX_EQ MAIN:%d PRE:%d POST:%d\n",
+                       hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
+               value = (0x1804 & ~0x3F3F);
+               value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+               value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+               wr32_epcs(hw, 0x18035, 0x00FF);
+               wr32_epcs(hw, 0x18055, 0x00FF);
+       }
+
+       if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
+               BP_LOG("Set KX TX_EQ MAIN:%d PRE:%d POST:%d\n",
+                       hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
+               value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
+                       hw->phy.ffe_pre;
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+               value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
+               value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
+               wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+
+               wr32_epcs(hw, 0x18035, 0x00FF);
+               wr32_epcs(hw, 0x18055, 0x00FF);
+       }
+}
+
 /**
  * txgbe_kr_handle - Handle the interrupt of auto-negotiation
  * @hw: pointer to hardware structure