u16 wwpn_prefix;
u32 num_rar_entries;
+ u32 max_tx_queues;
+ u32 max_rx_queues;
u8 san_mac_rar_index;
u64 orig_autoc; /* cached value of AUTOC */
u32 media_type;
u32 phy_semaphore_mask;
bool reset_disable;
+ bool multispeed_fiber;
bool qsfp_shared_i2c_bus;
u32 nw_mng_if_sel;
};
s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
};
+enum txgbe_isb_idx {
+ TXGBE_ISB_HEADER,
+ TXGBE_ISB_MISC,
+ TXGBE_ISB_VEC0,
+ TXGBE_ISB_VEC1,
+ TXGBE_ISB_MAX
+};
+
struct txgbe_hw {
void IOMEM *hw_addr;
void *back;