#ifndef _TXGBE_TYPE_H_
#define _TXGBE_TYPE_H_
+#define TXGBE_DCB_TC_MAX TXGBE_MAX_UP
+#define TXGBE_DCB_UP_MAX TXGBE_MAX_UP
+#define TXGBE_DCB_BWG_MAX TXGBE_MAX_UP
#define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
#define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
#define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */
#define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */
+#define TXGBE_NUM_POOL (64)
+#define TXGBE_PBTXSIZE_MAX 0x00028000 /* 160KB Packet Buffer */
+#define TXGBE_MAX_FTQF_FILTERS 128
+#define TXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
#define TXGBE_MAX_UP 8
#define TXGBE_MAX_QP (128)
#define TXGBE_MAX_UTA 128
+#define TXGBE_FDIR_INIT_DONE_POLL 10
+#define TXGBE_FDIRCMD_CMD_POLL 10
+
#define TXGBE_ALIGN 128 /* as intel did */
#include "txgbe_status.h"
struct txgbe_thermal_diode_data sensor[1];
};
+/* Packet buffer allocation strategies */
+enum {
+ PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
+#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
+ PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
+#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
+};
+
/* Physical layer type */
#define TXGBE_PHYSICAL_LAYER_UNKNOWN 0
#define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
#define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
#define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
+/* Software ATR hash keys */
+#define TXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
+#define TXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
+
+/* Software ATR input stream values and masks */
#define TXGBE_ATR_HASH_MASK 0x7fff
+#define TXGBE_ATR_L3TYPE_MASK 0x4
+#define TXGBE_ATR_L3TYPE_IPV4 0x0
+#define TXGBE_ATR_L3TYPE_IPV6 0x4
+#define TXGBE_ATR_L4TYPE_MASK 0x3
+#define TXGBE_ATR_L4TYPE_UDP 0x1
+#define TXGBE_ATR_L4TYPE_TCP 0x2
+#define TXGBE_ATR_L4TYPE_SCTP 0x3
+#define TXGBE_ATR_TUNNEL_MASK 0x10
+#define TXGBE_ATR_TUNNEL_ANY 0x10
+enum txgbe_atr_flow_type {
+ TXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
+ TXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
+ TXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
+ TXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
+ TXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
+ TXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
+ TXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
+ TXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17,
+};
+
+/* Flow Director ATR input struct. */
+struct txgbe_atr_input {
+ /*
+ * Byte layout in order, all values with MSB first:
+ *
+ * vm_pool - 1 byte
+ * flow_type - 1 byte
+ * vlan_id - 2 bytes
+ * src_ip - 16 bytes
+ * inner_mac - 6 bytes
+ * cloud_mode - 2 bytes
+ * tni_vni - 4 bytes
+ * dst_ip - 16 bytes
+ * src_port - 2 bytes
+ * dst_port - 2 bytes
+ * flex_bytes - 2 bytes
+ * bkt_hash - 2 bytes
+ */
+ u8 vm_pool;
+ u8 flow_type;
+ __be16 pkt_type;
+ __be32 dst_ip[4];
+ __be32 src_ip[4];
+ __be16 src_port;
+ __be16 dst_port;
+ __be16 flex_bytes;
+ __be16 bkt_hash;
+};
enum txgbe_eeprom_type {
txgbe_eeprom_unknown = 0,
txgbe_media_type_virtual
};
+/* Flow Control Settings */
+enum txgbe_fc_mode {
+ txgbe_fc_none = 0,
+ txgbe_fc_rx_pause,
+ txgbe_fc_tx_pause,
+ txgbe_fc_full,
+ txgbe_fc_default
+};
/* Smart Speed Settings */
#define TXGBE_SMARTSPEED_MAX_RETRIES 3
u16 instance_id;
};
+/* Flow control parameters */
+struct txgbe_fc_info {
+ u32 high_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl High-water */
+ u32 low_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl Low-water */
+ u16 pause_time; /* Flow Control Pause timer */
+ bool send_xon; /* Flow control send XON */
+ bool strict_ieee; /* Strict IEEE mode */
+ bool disable_fc_autoneg; /* Do not autonegotiate FC */
+ bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
+ enum txgbe_fc_mode current_mode; /* FC mode in effect */
+ enum txgbe_fc_mode requested_mode; /* FC mode requested by caller */
+};
+
/* Statistics counters collected by the MAC */
/* PB[] RxTx */
struct txgbe_pb_stats {
/* Manageability interface */
s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
- u8 ver, u16 len, char *driver_ver);
+ u8 ver, u16 len, const char *driver_ver);
s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw);
s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw);
void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map);
u32 mta_shadow[TXGBE_MAX_MTA];
s32 mc_filter_type;
u32 mcft_size;
+ u32 vft_size;
u32 num_rar_entries;
+ u32 rx_pb_size;
u32 max_tx_queues;
u32 max_rx_queues;
-
u8 san_mac_rar_index;
bool get_link_status;
u64 orig_autoc; /* cached value of AUTOC */
u32 link_mode;
};
+struct txgbe_mbx_stats {
+ u32 msgs_tx;
+ u32 msgs_rx;
+
+ u32 acks;
+ u32 reqs;
+ u32 rsts;
+};
+
struct txgbe_mbx_info {
void (*init_params)(struct txgbe_hw *hw);
s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id);
s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id);
s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
+
+ struct txgbe_mbx_stats stats;
+ u32 timeout;
+ u32 usec_delay;
+ u16 size;
};
enum txgbe_isb_idx {
void *back;
struct txgbe_mac_info mac;
struct txgbe_addr_filter_info addr_ctrl;
+ struct txgbe_fc_info fc;
struct txgbe_phy_info phy;
struct txgbe_link_info link;
struct txgbe_rom_info rom;
u16 vendor_id;
u16 subsystem_device_id;
u16 subsystem_vendor_id;
+ u8 revision_id;
bool adapter_stopped;
bool allow_unsupported_sfp;
bool need_crosstalk_fix;
void IOMEM *isb_mem;
u16 nb_rx_queues;
u16 nb_tx_queues;
+
+ u32 mode;
enum txgbe_link_status {
TXGBE_LINK_STATUS_NONE = 0,
TXGBE_LINK_STATUS_KX,
git.droids-corp.org / dpdk.git / blobdiff