/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015-2020
+ * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
*/
#ifndef _TXGBE_TYPE_H_
#define TXGBE_FDIR_INIT_DONE_POLL 10
#define TXGBE_FDIRCMD_CMD_POLL 10
#define TXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
+#define TXGBE_SPI_TIMEOUT 10000
#define TXGBE_ALIGN 128 /* as intel did */
s32 (*dmac_config)(struct txgbe_hw *hw);
s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
+ s32 (*kr_handle)(struct txgbe_hw *hw);
+ void (*bp_down_event)(struct txgbe_hw *hw);
+
enum txgbe_mac_type type;
u8 addr[ETH_ADDR_LEN];
u8 perm_addr[ETH_ADDR_LEN];
bool qsfp_shared_i2c_bus;
u32 nw_mng_if_sel;
u32 link_mode;
+
+ /* Some features need tri-state capability */
+ u16 ffe_set;
+ u16 ffe_main;
+ u16 ffe_pre;
+ u16 ffe_post;
};
#define TXGBE_DEVARG_BP_AUTO "auto_neg"
#define TXGBE_DEVARG_KR_POLL "poll"
#define TXGBE_DEVARG_KR_PRESENT "present"
#define TXGBE_DEVARG_KX_SGMII "sgmii"
+#define TXGBE_DEVARG_FFE_SET "ffe_set"
+#define TXGBE_DEVARG_FFE_MAIN "ffe_main"
+#define TXGBE_DEVARG_FFE_PRE "ffe_pre"
+#define TXGBE_DEVARG_FFE_POST "ffe_post"
static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_BP_AUTO,
TXGBE_DEVARG_KR_POLL,
TXGBE_DEVARG_KR_PRESENT,
TXGBE_DEVARG_KX_SGMII,
+ TXGBE_DEVARG_FFE_SET,
+ TXGBE_DEVARG_FFE_MAIN,
+ TXGBE_DEVARG_FFE_PRE,
+ TXGBE_DEVARG_FFE_POST,
+ NULL
};
struct txgbe_mbx_stats {
int api_version;
bool allow_unsupported_sfp;
bool need_crosstalk_fix;
+ bool dev_start;
struct txgbe_devargs devarg;
uint64_t isb_dma;
} qp_last[TXGBE_MAX_QP];
};
+struct txgbe_backplane_ability {
+ u32 next_page; /* Next Page (bit0) */
+ u32 link_ability; /* Link Ability (bit[7:0]) */
+ u32 fec_ability; /* FEC Request (bit1), FEC Enable (bit0) */
+ u32 current_link_mode; /* current link mode for local device */
+};
+
#include "txgbe_regs.h"
#include "txgbe_dummy.h"