net/txgbe: move firmware version get function to base code

[dpdk.git] / drivers / net / txgbe / base / txgbe_type.h

diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index ac36cb2..40c5516 100644 (file)
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -11,15 +11,23 @@
 #define TXGBE_LINK_UP_TIME     90 /* 9.0 Seconds */
 #define TXGBE_AUTO_NEG_TIME    45 /* 4.5 Seconds */
 
+#define TXGBE_RX_HDR_SIZE      256
+#define TXGBE_RX_BUF_SIZE      2048
+
 #define TXGBE_FRAME_SIZE_MAX   (9728) /* Maximum frame size, +FCS */
 #define TXGBE_FRAME_SIZE_DFT   (1518) /* Default frame size, +FCS */
 #define TXGBE_NUM_POOL         (64)
 #define TXGBE_PBTXSIZE_MAX     0x00028000 /* 160KB Packet Buffer */
+#define TXGBE_MAX_FTQF_FILTERS 128
 #define TXGBE_TXPKT_SIZE_MAX   0xA /* Max Tx Packet size */
 #define TXGBE_MAX_UP           8
 #define TXGBE_MAX_QP           (128)
 #define TXGBE_MAX_UTA          128
 
+#define TXGBE_FDIR_INIT_DONE_POLL              10
+#define TXGBE_FDIRCMD_CMD_POLL                 10
+#define TXGBE_VF_INIT_TIMEOUT  200 /* Number of retries to clear RSTI */
+
 #define TXGBE_ALIGN            128 /* as intel did */
 
 #include "txgbe_status.h"
@@ -64,7 +72,68 @@ enum {
 #define TXGBE_PHYSICAL_LAYER_10BASE_T          0x08000
 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX       0x10000
 
+/* Software ATR hash keys */
+#define TXGBE_ATR_BUCKET_HASH_KEY              0x3DAD14E2
+#define TXGBE_ATR_SIGNATURE_HASH_KEY           0x174D3614
+
+/* Software ATR input stream values and masks */
 #define TXGBE_ATR_HASH_MASK                    0x7fff
+#define TXGBE_ATR_L3TYPE_MASK                  0x4
+#define TXGBE_ATR_L3TYPE_IPV4                  0x0
+#define TXGBE_ATR_L3TYPE_IPV6                  0x4
+#define TXGBE_ATR_L4TYPE_MASK                  0x3
+#define TXGBE_ATR_L4TYPE_UDP                   0x1
+#define TXGBE_ATR_L4TYPE_TCP                   0x2
+#define TXGBE_ATR_L4TYPE_SCTP                  0x3
+#define TXGBE_ATR_TUNNEL_MASK                  0x10
+#define TXGBE_ATR_TUNNEL_ANY                   0x10
+enum txgbe_atr_flow_type {
+       TXGBE_ATR_FLOW_TYPE_IPV4                = 0x0,
+       TXGBE_ATR_FLOW_TYPE_UDPV4               = 0x1,
+       TXGBE_ATR_FLOW_TYPE_TCPV4               = 0x2,
+       TXGBE_ATR_FLOW_TYPE_SCTPV4              = 0x3,
+       TXGBE_ATR_FLOW_TYPE_IPV6                = 0x4,
+       TXGBE_ATR_FLOW_TYPE_UDPV6               = 0x5,
+       TXGBE_ATR_FLOW_TYPE_TCPV6               = 0x6,
+       TXGBE_ATR_FLOW_TYPE_SCTPV6              = 0x7,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4       = 0x10,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4      = 0x11,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4      = 0x12,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4     = 0x13,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6       = 0x14,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6      = 0x15,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6      = 0x16,
+       TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6     = 0x17,
+};
+
+/* Flow Director ATR input struct. */
+struct txgbe_atr_input {
+       /*
+        * Byte layout in order, all values with MSB first:
+        *
+        * vm_pool      - 1 byte
+        * flow_type    - 1 byte
+        * vlan_id      - 2 bytes
+        * src_ip       - 16 bytes
+        * inner_mac    - 6 bytes
+        * cloud_mode   - 2 bytes
+        * tni_vni      - 4 bytes
+        * dst_ip       - 16 bytes
+        * src_port     - 2 bytes
+        * dst_port     - 2 bytes
+        * flex_bytes   - 2 bytes
+        * bkt_hash     - 2 bytes
+        */
+       u8 vm_pool;
+       u8 flow_type;
+       __be16 pkt_type;
+       __be32 dst_ip[4];
+       __be32 src_ip[4];
+       __be16 src_port;
+       __be16 dst_port;
+       __be16 flex_bytes;
+       __be16 bkt_hash;
+};
 
 enum txgbe_eeprom_type {
        txgbe_eeprom_unknown = 0,
@@ -284,6 +353,7 @@ struct txgbe_hw_stats {
        u64 rx_management_packets;
        u64 tx_management_packets;
        u64 rx_management_dropped;
+       u64 rx_dma_drop;
        u64 rx_drop_packets;
 
        /* Basic Error */
@@ -577,6 +647,7 @@ struct txgbe_phy_info {
        s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
                                bool autoneg_wait_to_complete);
        s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
+       s32 (*get_fw_version)(struct txgbe_hw *hw, u32 *fw_version);
        s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
                                u8 dev_addr, u8 *data);
        s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
@@ -638,6 +709,7 @@ struct txgbe_mbx_info {
        struct txgbe_mbx_stats stats;
        u32 timeout;
        u32 usec_delay;
+       u32 v2p_mailbox;
        u16 size;
 };
 
@@ -665,7 +737,9 @@ struct txgbe_hw {
        u16 vendor_id;
        u16 subsystem_device_id;
        u16 subsystem_vendor_id;
+       u8 revision_id;
        bool adapter_stopped;
+       int api_version;
        bool allow_unsupported_sfp;
        bool need_crosstalk_fix;
 
@@ -674,6 +748,7 @@ struct txgbe_hw {
        u16 nb_rx_queues;
        u16 nb_tx_queues;
 
+       u32 fw_version;
        u32 mode;
        enum txgbe_link_status {
                TXGBE_LINK_STATUS_NONE = 0,
@@ -689,6 +764,7 @@ struct txgbe_hw {
        u32 q_rx_regs[128 * 4];
        u32 q_tx_regs[128 * 4];
        bool offset_loaded;
+       bool rx_loaded;
        struct {
                u64 rx_qp_packets;
                u64 tx_qp_packets;