#define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
#define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
+#define TXGBE_RX_HDR_SIZE 256
+#define TXGBE_RX_BUF_SIZE 2048
+
#define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */
#define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */
#define TXGBE_NUM_POOL (64)
#define TXGBE_FDIR_INIT_DONE_POLL 10
#define TXGBE_FDIRCMD_CMD_POLL 10
+#define TXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
#define TXGBE_ALIGN 128 /* as intel did */
#define TXGBE_ATR_L4TYPE_SCTP 0x3
#define TXGBE_ATR_TUNNEL_MASK 0x10
#define TXGBE_ATR_TUNNEL_ANY 0x10
+enum txgbe_atr_flow_type {
+ TXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
+ TXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
+ TXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
+ TXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
+ TXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
+ TXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
+ TXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
+ TXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16,
+ TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17,
+};
/* Flow Director ATR input struct. */
struct txgbe_atr_input {
struct txgbe_mbx_stats stats;
u32 timeout;
u32 usec_delay;
+ u32 v2p_mailbox;
u16 size;
};
u16 subsystem_vendor_id;
u8 revision_id;
bool adapter_stopped;
+ int api_version;
bool allow_unsupported_sfp;
bool need_crosstalk_fix;
u32 q_rx_regs[128 * 4];
u32 q_tx_regs[128 * 4];
bool offset_loaded;
+ bool rx_loaded;
struct {
u64 rx_qp_packets;
u64 tx_qp_packets;