#include <stdint.h>
#include <string.h>
#include <rte_common.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_pci.h>
#include <rte_interrupts.h>
#include <rte_log.h>
/* Unlock any pending hardware semaphore */
txgbe_swfw_lock_reset(hw);
+#ifdef RTE_LIB_SECURITY
+ /* Initialize security_ctx only for primary process*/
+ if (txgbe_ipsec_ctx_create(eth_dev))
+ return -ENOMEM;
+#endif
+
/* Initialize DCB configuration*/
memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
txgbe_dcb_init(hw, dcb_config);
/* initialize bandwidth configuration info */
memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
+ /* initialize Traffic Manager configuration */
+ txgbe_tm_conf_init(eth_dev);
+
return 0;
}
int status;
uint16_t vf, idx;
uint32_t *link_speeds;
+ struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
PMD_INIT_FUNC_TRACE();
txgbe_l2_tunnel_conf(dev);
txgbe_filter_restore(dev);
+ if (tm_conf->root && !tm_conf->committed)
+ PMD_DRV_LOG(WARNING,
+ "please call hierarchy_commit() "
+ "before starting the port");
+
/*
* Update link status right before return, because it may
* start link configuration process in a separate thread.
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
int vf;
+ struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
if (hw->adapter_stopped)
return 0;
intr_handle->intr_vec = NULL;
}
+ /* reset hierarchy commit */
+ tm_conf->committed = false;
+
adapter->rss_reta_updated = 0;
wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
/* clear all the filters list */
txgbe_filterlist_flush();
+ /* Remove all Traffic Manager configuration */
+ txgbe_tm_conf_uninit(dev);
+
+#ifdef RTE_LIB_SECURITY
+ rte_free(dev->security_ctx);
+#endif
+
return ret;
}
if (!mask)
continue;
- reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
+ reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
for (j = 0; j < 4; j++) {
if (RS8(mask, j, 0x1)) {
reta &= ~(MS32(8 * j, 0xFF));
8 * j, 0xFF);
}
}
- wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
+ wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
}
adapter->rss_reta_updated = 1;
if (!mask)
continue;
- reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
+ reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
for (j = 0; j < 4; j++) {
if (RS8(mask, j, 0x1))
reta_conf[idx].reta[shift + j] =
hw = TXGBE_DEV_HW(dev);
mc_addr_list = (u8 *)mc_addr_set;
- return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
+ return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
txgbe_dev_addr_list_itr, TRUE);
}
{
switch (mac_type) {
case txgbe_mac_raptor:
+ case txgbe_mac_raptor_vf:
return 1;
default:
return 0;
.timesync_write_time = txgbe_timesync_write_time,
.udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add,
.udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del,
+ .tm_ops_get = txgbe_tm_ops_get,
.tx_done_cleanup = txgbe_dev_tx_done_cleanup,
};