net/txgbe: support PTP

[dpdk.git] / drivers / net / txgbe / txgbe_ethdev.h

diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h
index ba9cab7..b439dd5 100644 (file)
--- a/drivers/net/txgbe/txgbe_ethdev.h
+++ b/drivers/net/txgbe/txgbe_ethdev.h
@@ -5,8 +5,11 @@
 #ifndef _TXGBE_ETHDEV_H_
 #define _TXGBE_ETHDEV_H_
 
+#include <stdint.h>
+
 #include "base/txgbe.h"
 #include "txgbe_ptypes.h"
+#include <rte_time.h>
 
 /* need update link, bit flag */
 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
@@ -127,6 +130,11 @@ struct txgbe_filter_info {
        struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
 };
 
+/* The configuration of bandwidth */
+struct txgbe_bw_conf {
+       uint8_t tc_num; /* Number of TCs. */
+};
+
 /*
  * Structure to store private data for each driver instance (for each port).
  */
@@ -137,11 +145,19 @@ struct txgbe_adapter {
        struct txgbe_stat_mappings  stat_mappings;
        struct txgbe_vfta           shadow_vfta;
        struct txgbe_hwstrip        hwstrip;
+       struct txgbe_dcb_config     dcb_config;
        struct txgbe_mirror_info    mr_data;
        struct txgbe_vf_info        *vfdata;
        struct txgbe_uta_info       uta_info;
        struct txgbe_filter_info    filter;
+       struct txgbe_bw_conf        bw_conf;
        bool rx_bulk_alloc_allowed;
+       struct rte_timecounter      systime_tc;
+       struct rte_timecounter      rx_tstamp_tc;
+       struct rte_timecounter      tx_tstamp_tc;
+
+       /* For RSS reta table update */
+       uint8_t rss_reta_updated;
 };
 
 #define TXGBE_DEV_ADAPTER(dev) \
@@ -165,6 +181,9 @@ struct txgbe_adapter {
 #define TXGBE_DEV_HWSTRIP(dev) \
        (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
 
+#define TXGBE_DEV_DCB_CONFIG(dev) \
+       (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
+
 #define TXGBE_DEV_VFDATA(dev) \
        (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
 
@@ -176,6 +195,9 @@ struct txgbe_adapter {
 
 #define TXGBE_DEV_FILTER(dev) \
        (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
+#define TXGBE_DEV_BW_CONF(dev) \
+       (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
+
 
 /*
  * RX/TX function prototypes
@@ -242,9 +264,21 @@ uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
                uint16_t nb_pkts);
 
+int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
+                             struct rte_eth_rss_conf *rss_conf);
+
+int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
+                               struct rte_eth_rss_conf *rss_conf);
+
+bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
+
 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
                               uint8_t queue, uint8_t msix_vector);
 
+void txgbe_configure_pb(struct rte_eth_dev *dev);
+void txgbe_configure_port(struct rte_eth_dev *dev);
+void txgbe_configure_dcb(struct rte_eth_dev *dev);
+
 int
 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
                int wait_to_complete);
@@ -256,6 +290,8 @@ void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
 
 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
 
+uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
+
 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
                            uint16_t tx_rate, uint64_t q_msk);
 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
@@ -298,6 +334,13 @@ txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
        return (i < TXGBE_ETF_ID_MAX ? i : -1);
 }
 
+/* High threshold controlling when to start sending XOFF frames. */
+#define TXGBE_FC_XOFF_HITH              128 /*KB*/
+/* Low threshold controlling when to start sending XON frames. */
+#define TXGBE_FC_XON_LOTH               64 /*KB*/
+
+/* Timer value included in XOFF frames. */
+#define TXGBE_FC_PAUSE_TIME 0x680
 
 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
 #define TXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
@@ -316,6 +359,21 @@ txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
 #define TXGBE_DEFAULT_TX_HTHRESH      0
 #define TXGBE_DEFAULT_TX_WTHRESH      0
 
+/* Additional timesync values. */
+#define NSEC_PER_SEC             1000000000L
+#define TXGBE_INCVAL_10GB        0xCCCCCC
+#define TXGBE_INCVAL_1GB         0x800000
+#define TXGBE_INCVAL_100         0xA00000
+#define TXGBE_INCVAL_10          0xC7F380
+#define TXGBE_INCVAL_FPGA        0x800000
+#define TXGBE_INCVAL_SHIFT_10GB  20
+#define TXGBE_INCVAL_SHIFT_1GB   18
+#define TXGBE_INCVAL_SHIFT_100   15
+#define TXGBE_INCVAL_SHIFT_10    12
+#define TXGBE_INCVAL_SHIFT_FPGA  17
+
+#define TXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
+
 /* store statistics names and its offset in stats structure */
 struct rte_txgbe_xstats_name_off {
        char name[RTE_ETH_XSTATS_NAME_SIZE];
@@ -326,6 +384,12 @@ const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
                                      struct rte_ether_addr *mc_addr_set,
                                      uint32_t nb_mc_addr);
+int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
+                       struct rte_eth_rss_reta_entry64 *reta_conf,
+                       uint16_t reta_size);
+int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
+                       struct rte_eth_rss_reta_entry64 *reta_conf,
+                       uint16_t reta_size);
 void txgbe_dev_setup_link_alarm_handler(void *param);
 void txgbe_read_stats_registers(struct txgbe_hw *hw,
                           struct txgbe_hw_stats *hw_stats);