examples/l3fwd: share queue size variables

[dpdk.git] / drivers / net / txgbe / txgbe_ipsec.c

diff --git a/drivers/net/txgbe/txgbe_ipsec.c b/drivers/net/txgbe/txgbe_ipsec.c
index 6e6006f..3ca3d85 100644 (file)
--- a/drivers/net/txgbe/txgbe_ipsec.c
+++ b/drivers/net/txgbe/txgbe_ipsec.c
@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015-2020
+ * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
  */
 
-#include <rte_ethdev_pci.h>
+#include <ethdev_pci.h>
 #include <rte_security_driver.h>
 #include <rte_cryptodev.h>
 
@@ -145,11 +146,11 @@ txgbe_crypto_add_sa(struct txgbe_crypto_session *ic_session)
                reg_val = TXGBE_IPSRXIDX_ENA | TXGBE_IPSRXIDX_WRITE |
                                TXGBE_IPSRXIDX_TB_IP | (ip_index << 3);
                if (priv->rx_ip_tbl[ip_index].ip.type == IPv4) {
-                       wr32(hw, TXGBE_IPSRXADDR(0), 0);
+                       uint32_t ipv4 = priv->rx_ip_tbl[ip_index].ip.ipv4;
+                       wr32(hw, TXGBE_IPSRXADDR(0), rte_cpu_to_be_32(ipv4));
                        wr32(hw, TXGBE_IPSRXADDR(1), 0);
                        wr32(hw, TXGBE_IPSRXADDR(2), 0);
-                       wr32(hw, TXGBE_IPSRXADDR(3),
-                                       priv->rx_ip_tbl[ip_index].ip.ipv4);
+                       wr32(hw, TXGBE_IPSRXADDR(3), 0);
                } else {
                        wr32(hw, TXGBE_IPSRXADDR(0),
                                        priv->rx_ip_tbl[ip_index].ip.ipv6[0]);
@@ -287,7 +288,7 @@ txgbe_crypto_remove_sa(struct rte_eth_dev *dev,
                        return -1;
                }
 
-               /* Disable and clear Rx SPI and key table entryes*/
+               /* Disable and clear Rx SPI and key table entries */
                reg_val = TXGBE_IPSRXIDX_WRITE |
                        TXGBE_IPSRXIDX_TB_SPI | (sa_index << 3);
                wr32(hw, TXGBE_IPSRXSPI, 0);
@@ -371,7 +372,7 @@ txgbe_crypto_create_session(void *device,
        aead_xform = &conf->crypto_xform->aead;
 
        if (conf->ipsec.direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {
-               if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SECURITY) {
+               if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
                        ic_session->op = TXGBE_OP_AUTHENTICATED_DECRYPTION;
                } else {
                        PMD_DRV_LOG(ERR, "IPsec decryption not enabled\n");
@@ -379,7 +380,7 @@ txgbe_crypto_create_session(void *device,
                        return -ENOTSUP;
                }
        } else {
-               if (dev_conf->txmode.offloads & DEV_TX_OFFLOAD_SECURITY) {
+               if (dev_conf->txmode.offloads & RTE_ETH_TX_OFFLOAD_SECURITY) {
                        ic_session->op = TXGBE_OP_AUTHENTICATED_ENCRYPTION;
                } else {
                        PMD_DRV_LOG(ERR, "IPsec encryption not enabled\n");
@@ -610,11 +611,11 @@ txgbe_crypto_enable_ipsec(struct rte_eth_dev *dev)
        tx_offloads = dev->data->dev_conf.txmode.offloads;
 
        /* sanity checks */
-       if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) {
+       if (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) {
                PMD_DRV_LOG(ERR, "RSC and IPsec not supported");
                return -1;
        }
-       if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
+       if (rx_offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
                PMD_DRV_LOG(ERR, "HW CRC strip needs to be enabled for IPsec");
                return -1;
        }
@@ -633,7 +634,7 @@ txgbe_crypto_enable_ipsec(struct rte_eth_dev *dev)
        reg |= TXGBE_SECRXCTL_CRCSTRIP;
        wr32(hw, TXGBE_SECRXCTL, reg);
 
-       if (rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
+       if (rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
                wr32m(hw, TXGBE_SECRXCTL, TXGBE_SECRXCTL_ODSA, 0);
                reg = rd32m(hw, TXGBE_SECRXCTL, TXGBE_SECRXCTL_ODSA);
                if (reg != 0) {
@@ -641,7 +642,7 @@ txgbe_crypto_enable_ipsec(struct rte_eth_dev *dev)
                        return -1;
                }
        }
-       if (tx_offloads & DEV_TX_OFFLOAD_SECURITY) {
+       if (tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) {
                wr32(hw, TXGBE_SECTXCTL, TXGBE_SECTXCTL_STFWD);
                reg = rd32(hw, TXGBE_SECTXCTL);
                if (reg != TXGBE_SECTXCTL_STFWD) {
@@ -655,6 +656,36 @@ txgbe_crypto_enable_ipsec(struct rte_eth_dev *dev)
        return 0;
 }
 
+int
+txgbe_crypto_add_ingress_sa_from_flow(const void *sess,
+                                     const void *ip_spec,
+                                     uint8_t is_ipv6)
+{
+       struct txgbe_crypto_session *ic_session =
+                       get_sec_session_private_data(sess);
+
+       if (ic_session->op == TXGBE_OP_AUTHENTICATED_DECRYPTION) {
+               if (is_ipv6) {
+                       const struct rte_flow_item_ipv6 *ipv6 = ip_spec;
+                       ic_session->src_ip.type = IPv6;
+                       ic_session->dst_ip.type = IPv6;
+                       rte_memcpy(ic_session->src_ip.ipv6,
+                                  ipv6->hdr.src_addr, 16);
+                       rte_memcpy(ic_session->dst_ip.ipv6,
+                                  ipv6->hdr.dst_addr, 16);
+               } else {
+                       const struct rte_flow_item_ipv4 *ipv4 = ip_spec;
+                       ic_session->src_ip.type = IPv4;
+                       ic_session->dst_ip.type = IPv4;
+                       ic_session->src_ip.ipv4 = ipv4->hdr.src_addr;
+                       ic_session->dst_ip.ipv4 = ipv4->hdr.dst_addr;
+               }
+               return txgbe_crypto_add_sa(ic_session);
+       }
+
+       return 0;
+}
+
 static struct rte_security_ops txgbe_security_ops = {
        .session_create = txgbe_crypto_create_session,
        .session_get_size = txgbe_crypto_session_get_size,