};
struct feature_fme_error0 {
-#define FME_ERROR0_MASK 0xFFUL
#define FME_ERROR0_MASK_DEFAULT 0x40UL /* pcode workaround */
union {
u64 csr;
struct {
u8 fabric_err:1; /* Fabric error */
u8 fabfifo_overflow:1; /* Fabric fifo overflow */
- u8 kticdc_parity_err:2;/* KTI CDC Parity Error */
- u8 iommu_parity_err:1; /* IOMMU Parity error */
+ u8 reserved2:3;
/* AFU PF/VF access mismatch detected */
u8 afu_acc_mode_err:1;
- u8 mbp_err:1; /* Indicates an MBP event */
+ u8 reserved6:1;
/* PCIE0 CDC Parity Error */
u8 pcie0cdc_parity_err:5;
/* PCIE1 CDC Parity Error */
u8 pcie1cdc_parity_err:5;
/* CVL CDC Parity Error */
u8 cvlcdc_parity_err:3;
- u64 rsvd:44; /* Reserved */
+ u8 fpgaseuerr:1;
+ u64 rsvd:43; /* Reserved */
};
};
};
u8 therm_catast_err:1;
/* Injected Catastrophic Error */
u8 injected_catast_err:1;
- u64 rsvd:52;
+ /* SEU error on BMC */
+ u8 bmc_seu_catast_err:1;
+ u64 rsvd:51;
};
};
};
u8 support_intr:1;
/* MSI-X vector table entry number */
u16 intr_vector_num:12;
- u64 rsvd:51; /* Reserved */
+ u64 rsvd:50; /* Reserved */
+ u64 seu_support:1;
};
};
};
struct feature_fme_ras_catfaterror ras_catfaterr;
struct feature_fme_ras_error_inj ras_error_inj;
struct feature_fme_error_capability fme_err_capability;
+ u64 seu_emr_l;
+ u64 seu_emr_h;
};
/* FME Partial Reconfiguration Control */
(((bts_hdr)->guid_h == GBS_GUID_H) && \
((bts_hdr)->guid_l == GBS_GUID_L))
+#define check_support(n) (n == 1 ? "support" : "no")
+
/* bitstream id definition */
struct fme_bitstream_id {
union {
u64 id;
struct {
- u64 hash:32;
- u64 interface:4;
- u64 reserved:12;
- u64 debug:4;
- u64 patch:4;
- u64 minor:4;
- u64 major:4;
+ u8 build_patch:8;
+ u8 build_minor:8;
+ u8 build_major:8;
+ u8 fvl_bypass:1;
+ u8 mac_lightweight:1;
+ u8 disagregate:1;
+ u8 lightweiht:1;
+ u8 seu:1;
+ u8 ptp:1;
+ u8 reserve:2;
+ u8 interface:4;
+ u32 afu_revision:12;
+ u8 patch:4;
+ u8 minor:4;
+ u8 major:4;
+ u8 reserved:4;
};
};
};
VC_2_2_25G = 4,
};
-struct ifpga_fme_board_info {
+enum pac_major {
+ VISTA_CREEK = 0,
+ RUSH_CREEK = 1,
+ DARBY_CREEK = 2,
+};
+
+enum pac_minor {
+ DCP_1_0 = 0,
+ DCP_1_1 = 1,
+ DCP_1_2 = 2,
+};
+
+struct opae_board_info {
+ enum pac_major major;
+ enum pac_minor minor;
enum board_interface type;
- u32 build_hash;
- u32 debug_version;
- u32 patch_version;
- u32 minor_version;
- u32 major_version;
+
+ /* PAC features */
+ u8 fvl_bypass;
+ u8 mac_lightweight;
+ u8 disaggregate;
+ u8 lightweight;
+ u8 seu;
+ u8 ptp;
+
+ u32 max10_version;
+ u32 nios_fw_version;
u32 nums_of_retimer;
u32 ports_per_retimer;
u32 nums_of_fvl;