#include "opae_intel_max10.h"
#include "opae_i2c.h"
#include "opae_at24_eeprom.h"
+#include "ifpga_sec_mgr.h"
#define PWR_THRESHOLD_MAX 0x7F
return 0;
}
+static int fme_hdr_get_port_type(struct ifpga_fme_hw *fme, u64 *port_type)
+{
+ struct feature_fme_header *fme_hdr
+ = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
+ struct feature_fme_port pt;
+ u32 port = (u32)((*port_type >> 32) & 0xffffffff);
+
+ pt.csr = readq(&fme_hdr->port[port]);
+ if (!pt.port_implemented)
+ return -ENODEV;
+ if (pt.afu_access_control)
+ *port_type |= 0x1;
+ else
+ *port_type &= ~0x1;
+
+ return 0;
+}
+
static int fme_hdr_get_cache_size(struct ifpga_fme_hw *fme, u64 *cache_size)
{
struct feature_fme_header *fme_hdr
return fme_hdr_get_bitstream_id(fme, &prop->data);
case FME_HDR_PROP_BITSTREAM_METADATA:
return fme_hdr_get_bitstream_metadata(fme, &prop->data);
+ case FME_HDR_PROP_PORT_TYPE:
+ return fme_hdr_get_port_type(fme, &prop->data);
}
return -ENOENT;
fme->board_info.nums_of_fvl,
fme->board_info.ports_per_fvl);
+ if (max10_sys_read(fme->max10_dev, FPGA_PAGE_INFO, &val))
+ return -EINVAL;
+ fme->board_info.boot_page = val & 0x7;
+
if (max10_sys_read(fme->max10_dev, MAX10_BUILD_VER, &val))
return -EINVAL;
- fme->board_info.max10_version = val & 0xffffff;
+ fme->board_info.max10_version = val;
if (max10_sys_read(fme->max10_dev, NIOS2_FW_VERSION, &val))
return -EINVAL;
- fme->board_info.nios_fw_version = val & 0xffffff;
+ fme->board_info.nios_fw_version = val;
dev_info(fme, "max10 version 0x%x, nios fw version 0x%x\n",
fme->board_info.max10_version,
return 0;
}
+static void init_spi_share_data(struct ifpga_fme_hw *fme,
+ struct altera_spi_device *spi)
+{
+ struct ifpga_hw *hw = (struct ifpga_hw *)fme->parent;
+ opae_share_data *sd = NULL;
+
+ if (hw && hw->adapter && hw->adapter->shm.ptr) {
+ dev_info(NULL, "transfer share data to spi\n");
+ sd = (opae_share_data *)hw->adapter->shm.ptr;
+ spi->mutex = &sd->spi_mutex;
+ spi->dtb_sz_ptr = &sd->dtb_size;
+ spi->dtb = sd->dtb;
+ } else {
+ spi->mutex = NULL;
+ spi->dtb_sz_ptr = NULL;
+ spi->dtb = NULL;
+ }
+}
+
static int fme_spi_init(struct ifpga_feature *feature)
{
struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
spi_master = altera_spi_alloc(feature->addr, TYPE_SPI);
if (!spi_master)
return -ENODEV;
+ init_spi_share_data(fme, spi_master);
altera_spi_init(spi_master);
goto spi_fail;
}
-
fme->max10_dev = max10;
/* SPI self test */
static int nios_spi_wait_init_done(struct altera_spi_device *dev)
{
u32 val = 0;
- unsigned long timeout = msecs_to_timer_cycles(10000);
+ unsigned long timeout = rte_get_timer_cycles() +
+ msecs_to_timer_cycles(10000);
unsigned long ticks;
int major_version;
+ int fecmode = FEC_MODE_NO;
if (spi_reg_read(dev, NIOS_VERSION, &val))
return -EIO;
- major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &
- NIOS_VERSION_MAJOR;
- dev_debug(dev, "A10 NIOS FW version %d\n", major_version);
+ major_version =
+ (val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT;
+ dev_info(dev, "A10 NIOS FW version %d\n", major_version);
if (major_version >= 3) {
/* read NIOS_INIT to check if PKVL INIT done or not */
if (spi_reg_read(dev, NIOS_INIT, &val))
return -EIO;
+ dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+
/* check if PKVLs are initialized already */
if (val & NIOS_INIT_DONE || val & NIOS_INIT_START)
goto nios_init_done;
/* start to config the default FEC mode */
- val = NIOS_INIT_START;
+ val = fecmode | NIOS_INIT_START;
if (spi_reg_write(dev, NIOS_INIT, val))
return -EIO;
do {
if (spi_reg_read(dev, NIOS_INIT, &val))
return -EIO;
- if (val)
+ if (val & NIOS_INIT_DONE)
break;
ticks = rte_get_timer_cycles();
if (time_after(ticks, timeout))
return -ETIMEDOUT;
msleep(100);
- } while (!val);
+ } while (1);
+
+ /* get the fecmode */
+ if (spi_reg_read(dev, NIOS_INIT, &val))
+ return -EIO;
+ dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+ fecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT;
+ dev_info(dev, "fecmode: 0x%x, %s\n", fecmode,
+ (fecmode == FEC_MODE_KR) ? "kr" :
+ ((fecmode == FEC_MODE_RS) ? "rs" : "no"));
return 0;
}
spi_master = altera_spi_alloc(feature->addr, TYPE_NIOS_SPI);
if (!spi_master)
return -ENODEV;
+ init_spi_share_data(fme, spi_master);
/**
* 1. wait A10 NIOS initial finished and
* release the SPI master to Host
*/
+ if (spi_master->mutex)
+ pthread_mutex_lock(spi_master->mutex);
+
ret = nios_spi_wait_init_done(spi_master);
if (ret != 0) {
dev_err(fme, "FME NIOS_SPI init fail\n");
+ if (spi_master->mutex)
+ pthread_mutex_unlock(spi_master->mutex);
goto release_dev;
}
if (nios_spi_check_error(spi_master))
dev_info(fme, "NIOS_SPI INIT done, but found some error\n");
+ if (spi_master->mutex)
+ pthread_mutex_unlock(spi_master->mutex);
+
/* 3. init the spi master*/
altera_spi_init(spi_master);
goto release_dev;
}
+ fme->max10_dev = max10;
+
max10->bus = hw->pci_data->bus;
fme_get_board_interface(fme);
- fme->max10_dev = max10;
mgr->sensor_list = &max10->opae_sensor_list;
/* SPI self test */
if (spi_self_checking(max10))
goto spi_fail;
+ ret = init_sec_mgr(fme);
+ if (ret) {
+ dev_err(fme, "security manager init fail\n");
+ goto spi_fail;
+ }
+
return ret;
spi_fail:
{
struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
+ release_sec_mgr(fme);
if (fme->max10_dev)
intel_max10_device_remove(fme->max10_dev);
}
return 0;
}
+static void init_i2c_mutex(struct ifpga_fme_hw *fme)
+{
+ struct ifpga_hw *hw = (struct ifpga_hw *)fme->parent;
+ struct altera_i2c_dev *i2c_dev;
+ opae_share_data *sd = NULL;
+
+ if (fme->i2c_master) {
+ i2c_dev = (struct altera_i2c_dev *)fme->i2c_master;
+ if (hw && hw->adapter && hw->adapter->shm.ptr) {
+ dev_info(NULL, "use multi-process mutex in i2c\n");
+ sd = (opae_share_data *)hw->adapter->shm.ptr;
+ i2c_dev->mutex = &sd->i2c_mutex;
+ } else {
+ dev_info(NULL, "use multi-thread mutex in i2c\n");
+ i2c_dev->mutex = &i2c_dev->lock;
+ }
+ }
+}
+
static int fme_i2c_init(struct ifpga_feature *feature)
{
struct feature_fme_i2c *i2c;
if (!fme->i2c_master)
return -ENODEV;
+ init_i2c_mutex(fme);
+
/* MAC ROM self test */
i2c_mac_rom_test(fme->i2c_master);
git.droids-corp.org / dpdk.git / blobdiff