/*-
* BSD LICENSE
*
- * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
+ * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */
#define MAX_PKT_BURST 32
-#define BURST_TX_DRAIN 200000ULL /* around 100us at 2 Ghz */
-
-#define SOCKET0 0
+#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
#define TX_QUEUE_FLUSH_MASK 0xFFFFFFFF
#define TSC_COUNT_LIMIT 1000
},
},
.txmode = {
- .mq_mode = ETH_DCB_NONE,
+ .mq_mode = ETH_MQ_TX_NONE,
},
};
get_output_port(uint8_t input_port)
{
RTE_BUILD_BUG_ON((RTE_MAX_ETHPORTS & 1) != 0);
- return (uint8_t)(input_port ^ 1);
+ /* Simple scheme to map consecutive ports. */
+ return (uint8_t)(input_port ^ 1);
}
/* main processing loop */
{
uint32_t lcoreid;
struct lcore_conf *qconf;
+ const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
lcoreid = rte_lcore_id();
qconf = &lcore_conf[lcoreid];
tsc = rte_rdtsc();
diff_tsc = tsc - qconf->tsc;
- if (unlikely(diff_tsc > BURST_TX_DRAIN)) {
+ if (unlikely(diff_tsc > drain_tsc)) {
nic_tx_flush_queues(qconf);
crypto_flush_tx_queue(lcoreid);
qconf->tsc = tsc;