-/*-
- * BSD LICENSE
- *
- * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2016 Intel Corporation
*/
#include <inttypes.h>
#include <rte_ip.h>
#include <rte_eal.h>
#include <rte_malloc.h>
+#include <rte_bus_pci.h>
#include "app.h"
#include "pipeline.h"
app_init_core_map(struct app_params *app)
{
APP_LOG(app, HIGH, "Initializing CPU core map ...");
- app->core_map = cpu_core_map_init(4, 32, 4, 0);
+ app->core_map = cpu_core_map_init(RTE_MAX_NUMA_NODES, RTE_MAX_LCORE,
+ 4, 0);
if (app->core_map == NULL)
rte_panic("Cannot create CPU core map\n");
app->eal_argv[n_args++] = strdup(buffer);
}
- if ((p->xen_dom0_present) && (p->xen_dom0)) {
- snprintf(buffer, sizeof(buffer), "--xen-dom0");
- app->eal_argv[n_args++] = strdup(buffer);
- }
-
snprintf(buffer, sizeof(buffer), "--");
app->eal_argv[n_args++] = strdup(buffer);
/* PMD link up */
status = rte_eth_dev_set_link_up(cp->pmd_id);
- if (status < 0)
+ /* Do not panic if PMD does not provide link up functionality */
+ if (status < 0 && status != -ENOTSUP)
rte_panic("%s (%" PRIu32 "): PMD set link up error %"
PRId32 "\n", cp->name, cp->pmd_id, status);
/* PMD link down */
status = rte_eth_dev_set_link_down(cp->pmd_id);
- if (status < 0)
+ /* Do not panic if PMD does not provide link down functionality */
+ if (status < 0 && status != -ENOTSUP)
rte_panic("%s (%" PRIu32 "): PMD set link down error %"
PRId32 "\n", cp->name, cp->pmd_id, status);
uint32_t i;
if (is_any_swq_frag_or_ras(app)) {
- for (i = 0; i < app->n_pktq_hwq_out; i++) {
- struct app_pktq_hwq_out_params *p_txq = &app->hwq_out_params[i];
-
- p_txq->conf.txq_flags &= ~ETH_TXQ_FLAGS_NOMULTSEGS;
+ for (i = 0; i < app->n_links; i++) {
+ struct app_link_params *p_link = &app->link_params[i];
+ p_link->conf.txmode.offloads |=
+ DEV_TX_OFFLOAD_MULTI_SEGS;
}
}
}
for (i = 0; i < app->n_links; i++) {
struct app_link_params *p_link = &app->link_params[i];
+ struct rte_eth_dev_info dev_info;
uint32_t link_id, n_hwq_in, n_hwq_out, j;
int status;
n_hwq_out);
/* LINK */
+ rte_eth_dev_info_get(p_link->pmd_id, &dev_info);
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE)
+ p_link->conf.txmode.offloads |=
+ DEV_TX_OFFLOAD_MBUF_FAST_FREE;
status = rte_eth_dev_configure(
p_link->pmd_id,
n_hwq_in,
struct app_pktq_hwq_in_params *p_rxq =
&app->hwq_in_params[j];
uint32_t rxq_link_id, rxq_queue_id;
+ uint16_t nb_rxd = p_rxq->size;
sscanf(p_rxq->name, "RXQ%" PRIu32 ".%" PRIu32,
&rxq_link_id, &rxq_queue_id);
if (rxq_link_id != link_id)
continue;
+ status = rte_eth_dev_adjust_nb_rx_tx_desc(
+ p_link->pmd_id,
+ &nb_rxd,
+ NULL);
+ if (status < 0)
+ rte_panic("%s (%" PRIu32 "): "
+ "%s adjust number of Rx descriptors "
+ "error (%" PRId32 ")\n",
+ p_link->name,
+ p_link->pmd_id,
+ p_rxq->name,
+ status);
+
+ p_rxq->conf.offloads = p_link->conf.rxmode.offloads;
status = rte_eth_rx_queue_setup(
p_link->pmd_id,
rxq_queue_id,
- p_rxq->size,
+ nb_rxd,
app_get_cpu_socket_id(p_link->pmd_id),
&p_rxq->conf,
app->mempool[p_rxq->mempool_id]);
struct app_pktq_hwq_out_params *p_txq =
&app->hwq_out_params[j];
uint32_t txq_link_id, txq_queue_id;
+ uint16_t nb_txd = p_txq->size;
sscanf(p_txq->name, "TXQ%" PRIu32 ".%" PRIu32,
&txq_link_id, &txq_queue_id);
if (txq_link_id != link_id)
continue;
+ status = rte_eth_dev_adjust_nb_rx_tx_desc(
+ p_link->pmd_id,
+ NULL,
+ &nb_txd);
+ if (status < 0)
+ rte_panic("%s (%" PRIu32 "): "
+ "%s adjust number of Tx descriptors "
+ "error (%" PRId32 ")\n",
+ p_link->name,
+ p_link->pmd_id,
+ p_txq->name,
+ status);
+
+ p_txq->conf.offloads = p_link->conf.txmode.offloads;
status = rte_eth_tx_queue_setup(
p_link->pmd_id,
txq_queue_id,
- p_txq->size,
+ nb_txd,
app_get_cpu_socket_id(p_link->pmd_id),
&p_txq->conf);
if (status < 0)
#ifdef RTE_LIBRTE_KNI
static int
-kni_config_network_interface(uint8_t port_id, uint8_t if_up) {
+kni_config_network_interface(uint16_t port_id, uint8_t if_up) {
int ret = 0;
if (port_id >= rte_eth_dev_count())
}
static int
-kni_change_mtu(uint8_t port_id, unsigned new_mtu) {
+kni_change_mtu(uint16_t port_id, unsigned int new_mtu) {
int ret;
if (port_id >= rte_eth_dev_count())