.nb_event_port_enqueue_depth = 128
};
struct rte_event_dev_info dev_info;
- uint8_t disable_implicit_release;
const uint8_t event_d_id = 0; /* Always use first event device only */
uint32_t event_queue_cfg = 0;
uint16_t ethdev_count = 0;
/* Event device configurtion */
rte_event_dev_info_get(event_d_id, &dev_info);
- disable_implicit_release = !!(dev_info.event_dev_cap &
- RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE);
- evt_rsrc->disable_implicit_release =
- disable_implicit_release;
+ /* Enable implicit release */
+ if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE)
+ evt_rsrc->disable_implicit_release = 0;
if (dev_info.event_dev_cap & RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES)
event_queue_cfg |= RTE_EVENT_QUEUE_CFG_ALL_TYPES;
event_d_conf.nb_event_port_enqueue_depth =
dev_info.max_event_port_enqueue_depth;
- num_workers = rte_lcore_count();
+ /* Ignore Main core. */
+ num_workers = rte_lcore_count() - 1;
if (dev_info.max_event_ports < num_workers)
num_workers = dev_info.max_event_ports;
if (!evt_rsrc->evp.event_p_id)
rte_panic("Failed to allocate memory for Event Ports\n");
- rte_event_port_default_conf_get(event_d_id, 0, &def_p_conf);
+ ret = rte_event_port_default_conf_get(event_d_id, 0, &def_p_conf);
+ if (ret < 0)
+ rte_panic("Error to get default configuration of event port\n");
+
if (def_p_conf.new_event_threshold < event_p_conf.new_event_threshold)
event_p_conf.new_event_threshold =
def_p_conf.new_event_threshold;
if (def_p_conf.enqueue_depth < event_p_conf.enqueue_depth)
event_p_conf.enqueue_depth = def_p_conf.enqueue_depth;
- event_p_conf.disable_implicit_release =
- evt_rsrc->disable_implicit_release;
+ event_p_conf.event_port_cfg = 0;
+ if (evt_rsrc->disable_implicit_release)
+ event_p_conf.event_port_cfg |=
+ RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL;
for (event_p_id = 0; event_p_id < evt_rsrc->evp.nb_ports;
event_p_id++) {
uint8_t event_q_id = 0;
int32_t ret;
- rte_event_queue_default_conf_get(event_d_id, event_q_id, &def_q_conf);
+ ret = rte_event_queue_default_conf_get(event_d_id, event_q_id,
+ &def_q_conf);
+ if (ret < 0)
+ rte_panic("Error to get default config of event queue\n");
if (def_q_conf.nb_atomic_flows < event_q_conf.nb_atomic_flows)
event_q_conf.nb_atomic_flows = def_q_conf.nb_atomic_flows;
l2fwd_rx_tx_adapter_setup_internal_port(struct l2fwd_resources *rsrc)
{
struct l2fwd_event_resources *evt_rsrc = rsrc->evt_rsrc;
- struct rte_event_eth_rx_adapter_queue_conf eth_q_conf = {
- .rx_queue_flags = 0,
- .ev = {
- .queue_id = 0,
- .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
- }
- };
+ struct rte_event_eth_rx_adapter_queue_conf eth_q_conf;
uint8_t event_d_id = evt_rsrc->event_d_id;
uint16_t adapter_id = 0;
uint16_t nb_adapter = 0;
uint8_t q_id = 0;
int ret;
+ memset(ð_q_conf, 0, sizeof(eth_q_conf));
+ eth_q_conf.ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
+
RTE_ETH_FOREACH_DEV(port_id) {
if ((rsrc->enabled_port_mask & (1 << port_id)) == 0)
continue;
rte_panic("Failed to allocate memery for Rx adapter\n");
}
-
+ /* Assigned ethernet port. 8< */
RTE_ETH_FOREACH_DEV(port_id) {
if ((rsrc->enabled_port_mask & (1 << port_id)) == 0)
continue;
+
+ if (rsrc->evt_vec.enabled) {
+ uint32_t cap;
+
+ if (rte_event_eth_rx_adapter_caps_get(event_d_id,
+ port_id, &cap))
+ rte_panic(
+ "Failed to get event rx adapter capability");
+
+ if (cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR) {
+ eth_q_conf.vector_sz = rsrc->evt_vec.size;
+ eth_q_conf.vector_timeout_ns =
+ rsrc->evt_vec.timeout_ns;
+ eth_q_conf.vector_mp = rsrc->evt_vec_pool;
+ eth_q_conf.rx_queue_flags |=
+ RTE_EVENT_ETH_RX_ADAPTER_QUEUE_EVENT_VECTOR;
+ } else {
+ rte_panic(
+ "Rx adapter doesn't support event vector");
+ }
+ }
+
ret = rte_event_eth_rx_adapter_create(adapter_id, event_d_id,
&evt_rsrc->def_p_conf);
if (ret)
evt_rsrc->tx_adptr.tx_adptr[adapter_id] = adapter_id;
adapter_id++;
}
+ /* >8 End of assigned ethernet port. */
}
void