common/cnxk: use computed value for WQE skip

[dpdk.git] / lib / ipsec / sa.h

diff --git a/lib/ipsec/sa.h b/lib/ipsec/sa.h
index 1bffe75..ce4af8c 100644 (file)
--- a/lib/ipsec/sa.h
+++ b/lib/ipsec/sa.h
@@ -5,7 +5,6 @@
 #ifndef _SA_H_
 #define _SA_H_
 
-#include <rte_rwlock.h>
 
 #define IPSEC_MAX_HDR_SIZE     64
 #define IPSEC_MAX_IV_SIZE      16
@@ -19,7 +18,10 @@ enum {
        IPSEC_PAD_AES_CBC = IPSEC_MAX_IV_SIZE,
        IPSEC_PAD_AES_CTR = IPSEC_PAD_DEFAULT,
        IPSEC_PAD_AES_GCM = IPSEC_PAD_DEFAULT,
+       IPSEC_PAD_AES_CCM = IPSEC_PAD_DEFAULT,
+       IPSEC_PAD_CHACHA20_POLY1305 = IPSEC_PAD_DEFAULT,
        IPSEC_PAD_NULL = IPSEC_PAD_DEFAULT,
+       IPSEC_PAD_AES_GMAC = IPSEC_PAD_DEFAULT,
 };
 
 /* iv sizes for different algorithms */
@@ -57,7 +59,7 @@ union sym_op_data {
 struct replay_sqn {
        rte_rwlock_t rwl;
        uint64_t sqn;
-       __extension__ uint64_t window[0];
+       __extension__ uint64_t window[];
 };
 
 /*IPSEC SA supported algorithms */
@@ -67,6 +69,9 @@ enum sa_algo_type     {
        ALGO_TYPE_AES_CBC,
        ALGO_TYPE_AES_CTR,
        ALGO_TYPE_AES_GCM,
+       ALGO_TYPE_AES_CCM,
+       ALGO_TYPE_CHACHA20_POLY1305,
+       ALGO_TYPE_AES_GMAC,
        ALGO_TYPE_MAX
 };
 
@@ -116,7 +121,7 @@ struct rte_ipsec_sa {
         * In case of SA handled by multiple threads *sqn* cacheline
         * could be shared by multiple cores.
         * To minimise performance impact, we try to locate in a separate
-        * place from other frequently accesed data.
+        * place from other frequently accessed data.
         */
        union {
                uint64_t outb;
@@ -126,6 +131,15 @@ struct rte_ipsec_sa {
                        struct replay_sqn *rsn[REPLAY_SQN_NUM];
                } inb;
        } sqn;
+       /* Statistics */
+       struct {
+               uint64_t count;
+               uint64_t bytes;
+               struct {
+                       uint64_t count;
+                       uint64_t authentication_failed;
+               } errors;
+       } statistics;
 
 } __rte_cache_aligned;