net/mlx5: make tunnel hub list thread safe
[dpdk.git] / lib / librte_acl / rte_acl.c
index bd7247c..4e693b2 100644 (file)
@@ -2,9 +2,11 @@
  * Copyright(c) 2010-2014 Intel Corporation
  */
 
+#include <rte_eal_memconfig.h>
 #include <rte_string_fns.h>
 #include <rte_acl.h>
 #include <rte_tailq.h>
+#include <rte_vect.h>
 
 #include "acl.h"
 
@@ -15,7 +17,32 @@ static struct rte_tailq_elem rte_acl_tailq = {
 };
 EAL_REGISTER_TAILQ(rte_acl_tailq)
 
-#ifndef RTE_ARCH_X86
+#ifndef CC_AVX512_SUPPORT
+/*
+ * If the compiler doesn't support AVX512 instructions,
+ * then the dummy one would be used instead for AVX512 classify method.
+ */
+int
+rte_acl_classify_avx512x16(__rte_unused const struct rte_acl_ctx *ctx,
+       __rte_unused const uint8_t **data,
+       __rte_unused uint32_t *results,
+       __rte_unused uint32_t num,
+       __rte_unused uint32_t categories)
+{
+       return -ENOTSUP;
+}
+
+int
+rte_acl_classify_avx512x32(__rte_unused const struct rte_acl_ctx *ctx,
+       __rte_unused const uint8_t **data,
+       __rte_unused uint32_t *results,
+       __rte_unused uint32_t num,
+       __rte_unused uint32_t categories)
+{
+       return -ENOTSUP;
+}
+#endif
+
 #ifndef CC_AVX2_SUPPORT
 /*
  * If the compiler doesn't support AVX2 instructions,
@@ -32,6 +59,7 @@ rte_acl_classify_avx2(__rte_unused const struct rte_acl_ctx *ctx,
 }
 #endif
 
+#ifndef RTE_ARCH_X86
 int
 rte_acl_classify_sse(__rte_unused const struct rte_acl_ctx *ctx,
        __rte_unused const uint8_t **data,
@@ -44,7 +72,6 @@ rte_acl_classify_sse(__rte_unused const struct rte_acl_ctx *ctx,
 #endif
 
 #ifndef RTE_ARCH_ARM
-#ifndef RTE_ARCH_ARM64
 int
 rte_acl_classify_neon(__rte_unused const struct rte_acl_ctx *ctx,
        __rte_unused const uint8_t **data,
@@ -55,7 +82,6 @@ rte_acl_classify_neon(__rte_unused const struct rte_acl_ctx *ctx,
        return -ENOTSUP;
 }
 #endif
-#endif
 
 #ifndef RTE_ARCH_PPC_64
 int
@@ -76,57 +102,189 @@ static const rte_acl_classify_t classify_fns[] = {
        [RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,
        [RTE_ACL_CLASSIFY_NEON] = rte_acl_classify_neon,
        [RTE_ACL_CLASSIFY_ALTIVEC] = rte_acl_classify_altivec,
+       [RTE_ACL_CLASSIFY_AVX512X16] = rte_acl_classify_avx512x16,
+       [RTE_ACL_CLASSIFY_AVX512X32] = rte_acl_classify_avx512x32,
 };
 
-/* by default, use always available scalar code path. */
-static enum rte_acl_classify_alg rte_acl_default_classify =
-       RTE_ACL_CLASSIFY_SCALAR;
-
-static void
-rte_acl_set_default_classify(enum rte_acl_classify_alg alg)
+/*
+ * Helper function for acl_check_alg.
+ * Check support for ARM specific classify methods.
+ */
+static int
+acl_check_alg_arm(enum rte_acl_classify_alg alg)
 {
-       rte_acl_default_classify = alg;
+       if (alg == RTE_ACL_CLASSIFY_NEON) {
+#if defined(RTE_ARCH_ARM64)
+               if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128)
+                       return 0;
+#elif defined(RTE_ARCH_ARM)
+               if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) &&
+                               rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128)
+                       return 0;
+#endif
+               return -ENOTSUP;
+       }
+
+       return -EINVAL;
 }
 
-extern int
-rte_acl_set_ctx_classify(struct rte_acl_ctx *ctx, enum rte_acl_classify_alg alg)
+/*
+ * Helper function for acl_check_alg.
+ * Check support for PPC specific classify methods.
+ */
+static int
+acl_check_alg_ppc(enum rte_acl_classify_alg alg)
 {
-       if (ctx == NULL || (uint32_t)alg >= RTE_DIM(classify_fns))
-               return -EINVAL;
+       if (alg == RTE_ACL_CLASSIFY_ALTIVEC) {
+#if defined(RTE_ARCH_PPC_64)
+               if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128)
+                       return 0;
+#endif
+               return -ENOTSUP;
+       }
 
-       ctx->alg = alg;
-       return 0;
+       return -EINVAL;
+}
+
+#ifdef CC_AVX512_SUPPORT
+static int
+acl_check_avx512_cpu_flags(void)
+{
+       return (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&
+                       rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) &&
+                       rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) &&
+                       rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW));
 }
+#endif
 
 /*
- * Select highest available classify method as default one.
- * Note that CLASSIFY_AVX2 should be set as a default only
- * if both conditions are met:
- * at build time compiler supports AVX2 and target cpu supports AVX2.
+ * Helper function for acl_check_alg.
+ * Check support for x86 specific classify methods.
  */
-RTE_INIT(rte_acl_init)
+static int
+acl_check_alg_x86(enum rte_acl_classify_alg alg)
 {
-       enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;
+       if (alg == RTE_ACL_CLASSIFY_AVX512X32) {
+#ifdef CC_AVX512_SUPPORT
+               if (acl_check_avx512_cpu_flags() != 0 &&
+                       rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
+                       return 0;
+#endif
+               return -ENOTSUP;
+       }
 
-#if defined(RTE_ARCH_ARM64)
-       alg =  RTE_ACL_CLASSIFY_NEON;
-#elif defined(RTE_ARCH_ARM)
-       if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
-               alg =  RTE_ACL_CLASSIFY_NEON;
-#elif defined(RTE_ARCH_PPC_64)
-       alg = RTE_ACL_CLASSIFY_ALTIVEC;
-#else
+       if (alg == RTE_ACL_CLASSIFY_AVX512X16) {
+#ifdef CC_AVX512_SUPPORT
+               if (acl_check_avx512_cpu_flags() != 0 &&
+                       rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
+                       return 0;
+#endif
+               return -ENOTSUP;
+       }
+
+       if (alg == RTE_ACL_CLASSIFY_AVX2) {
 #ifdef CC_AVX2_SUPPORT
-       if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
-               alg = RTE_ACL_CLASSIFY_AVX2;
-       else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
-#else
-       if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
+               if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) &&
+                               rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
+                       return 0;
 #endif
-               alg = RTE_ACL_CLASSIFY_SSE;
+               return -ENOTSUP;
+       }
 
+       if (alg == RTE_ACL_CLASSIFY_SSE) {
+#ifdef RTE_ARCH_X86
+               if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) &&
+                               rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128)
+                       return 0;
 #endif
-       rte_acl_set_default_classify(alg);
+               return -ENOTSUP;
+       }
+
+       return -EINVAL;
+}
+
+/*
+ * Check if input alg is supported by given platform/binary.
+ * Note that both conditions should be met:
+ * - at build time compiler supports ISA used by given methods
+ * - at run time target cpu supports necessary ISA.
+ */
+static int
+acl_check_alg(enum rte_acl_classify_alg alg)
+{
+       switch (alg) {
+       case RTE_ACL_CLASSIFY_NEON:
+               return acl_check_alg_arm(alg);
+       case RTE_ACL_CLASSIFY_ALTIVEC:
+               return acl_check_alg_ppc(alg);
+       case RTE_ACL_CLASSIFY_AVX512X32:
+       case RTE_ACL_CLASSIFY_AVX512X16:
+       case RTE_ACL_CLASSIFY_AVX2:
+       case RTE_ACL_CLASSIFY_SSE:
+               return acl_check_alg_x86(alg);
+       /* scalar method is supported on all platforms */
+       case RTE_ACL_CLASSIFY_SCALAR:
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
+/*
+ * Get preferred alg for given platform.
+ */
+static enum rte_acl_classify_alg
+acl_get_best_alg(void)
+{
+       /*
+        * array of supported methods for each platform.
+        * Note that order is important - from most to less preferable.
+        */
+       static const enum rte_acl_classify_alg alg[] = {
+#if defined(RTE_ARCH_ARM)
+               RTE_ACL_CLASSIFY_NEON,
+#elif defined(RTE_ARCH_PPC_64)
+               RTE_ACL_CLASSIFY_ALTIVEC,
+#elif defined(RTE_ARCH_X86)
+               RTE_ACL_CLASSIFY_AVX512X32,
+               RTE_ACL_CLASSIFY_AVX512X16,
+               RTE_ACL_CLASSIFY_AVX2,
+               RTE_ACL_CLASSIFY_SSE,
+#endif
+               RTE_ACL_CLASSIFY_SCALAR,
+       };
+
+       uint32_t i;
+
+       /* find best possible alg */
+       for (i = 0; i != RTE_DIM(alg) && acl_check_alg(alg[i]) != 0; i++)
+               ;
+
+       /* we always have to find something suitable */
+       RTE_VERIFY(i != RTE_DIM(alg));
+       return alg[i];
+}
+
+extern int
+rte_acl_set_ctx_classify(struct rte_acl_ctx *ctx, enum rte_acl_classify_alg alg)
+{
+       int32_t rc;
+
+       /* formal parameters check */
+       if (ctx == NULL || (uint32_t)alg >= RTE_DIM(classify_fns))
+               return -EINVAL;
+
+       /* user asked us to select the *best* one */
+       if (alg == RTE_ACL_CLASSIFY_DEFAULT)
+               alg = acl_get_best_alg();
+
+       /* check that given alg is supported */
+       rc = acl_check_alg(alg);
+       if (rc != 0)
+               return rc;
+
+       ctx->alg = alg;
+       return 0;
 }
 
 int
@@ -261,7 +419,7 @@ rte_acl_create(const struct rte_acl_param *param)
                ctx->max_rules = param->max_rule_num;
                ctx->rule_sz = param->rule_size;
                ctx->socket_id = param->socket_id;
-               ctx->alg = rte_acl_default_classify;
+               ctx->alg = acl_get_best_alg();
                strlcpy(ctx->name, param->name, sizeof(ctx->name));
 
                te->data = (void *) ctx;
@@ -360,6 +518,7 @@ rte_acl_dump(const struct rte_acl_ctx *ctx)
        printf("acl context <%s>@%p\n", ctx->name, ctx);
        printf("  socket_id=%"PRId32"\n", ctx->socket_id);
        printf("  alg=%"PRId32"\n", ctx->alg);
+       printf("  first_load_sz=%"PRIu32"\n", ctx->first_load_sz);
        printf("  max_rules=%"PRIu32"\n", ctx->max_rules);
        printf("  rule_size=%"PRIu32"\n", ctx->rule_sz);
        printf("  num_rules=%"PRIu32"\n", ctx->num_rules);