/**< AES-NI Multi buffer PMD device name */
#define CRYPTODEV_NAME_AESNI_GCM_PMD crypto_aesni_gcm
/**< AES-NI GCM PMD device name */
+#define CRYPTODEV_NAME_OPENSSL_PMD crypto_openssl
+/**< Open SSL Crypto PMD device name */
#define CRYPTODEV_NAME_QAT_SYM_PMD crypto_qat
/**< Intel QAT Symmetric Crypto PMD device name */
#define CRYPTODEV_NAME_SNOW3G_PMD crypto_snow3g
/**< SNOW 3G PMD device name */
#define CRYPTODEV_NAME_KASUMI_PMD crypto_kasumi
/**< KASUMI PMD device name */
+#define CRYPTODEV_NAME_ZUC_PMD crypto_zuc
+/**< KASUMI PMD device name */
/** Crypto device type */
enum rte_cryptodev_type {
RTE_CRYPTODEV_QAT_SYM_PMD, /**< QAT PMD Symmetric Crypto */
RTE_CRYPTODEV_SNOW3G_PMD, /**< SNOW 3G PMD */
RTE_CRYPTODEV_KASUMI_PMD, /**< KASUMI PMD */
+ RTE_CRYPTODEV_ZUC_PMD, /**< ZUC PMD */
+ RTE_CRYPTODEV_OPENSSL_PMD, /**< OpenSSL PMD */
};
extern const char **rte_cyptodev_names;
enum rte_cryptodev_type dev_type;
/**< Crypto device type */
- enum pmd_type pmd_type;
- /**< PMD type - PDEV / VDEV */
struct rte_cryptodev_cb_list link_intr_cbs;
/**< User application callback for interrupts if present */
} __rte_aligned(8);
/**< Public symmetric session details */
- char _private[];
+ __extension__ char _private[0];
/**< Private session material */
};