eal: remove redundant atomic API description

[dpdk.git] / lib / librte_eal / common / include / arch / ppc_64 / rte_atomic.h

diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index fb4fccb..d6d4014 100644 (file)
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -49,37 +49,11 @@ extern "C" {
 #include <stdint.h>
 #include "generic/rte_atomic.h"
 
-/**
- * General memory barrier.
- *
- * Guarantees that the LOAD and STORE operations generated before the
- * barrier occur before the LOAD and STORE operations generated after.
- */
-#define        rte_mb()  {asm volatile("sync" : : : "memory"); }
+#define        rte_mb()  asm volatile("sync" : : : "memory")
 
-/**
- * Write memory barrier.
- *
- * Guarantees that the STORE operations generated before the barrier
- * occur before the STORE operations generated after.
- */
-#ifdef RTE_ARCH_64
-#define        rte_wmb() {asm volatile("lwsync" : : : "memory"); }
-#else
-#define        rte_wmb() {asm volatile("sync" : : : "memory"); }
-#endif
+#define        rte_wmb() asm volatile("sync" : : : "memory")
 
-/**
- * Read memory barrier.
- *
- * Guarantees that the LOAD operations generated before the barrier
- * occur before the LOAD operations generated after.
- */
-#ifdef RTE_ARCH_64
-#define        rte_rmb() {asm volatile("lwsync" : : : "memory"); }
-#else
-#define        rte_rmb() {asm volatile("sync" : : : "memory"); }
-#endif
+#define        rte_rmb() asm volatile("sync" : : : "memory")
 
 #define rte_smp_mb() rte_mb()
 
@@ -87,6 +61,16 @@ extern "C" {
 
 #define rte_smp_rmb() rte_rmb()
 
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
+#define rte_cio_wmb() rte_wmb()
+
+#define rte_cio_rmb() rte_rmb()
+
 /*------------------------- 16 bit atomic operations -------------------------*/
 /* To be compatible with Power7, use GCC built-in functions for 16 bit
  * operations */
@@ -126,6 +110,12 @@ static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
        return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
 }
 
+static inline uint16_t
+rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
+{
+       return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);
+}
+
 /*------------------------- 32 bit atomic operations -------------------------*/
 
 static inline int
@@ -227,6 +217,13 @@ static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
 
        return ret == 0;
 }
+
+static inline uint32_t
+rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
+{
+       return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
+}
+
 /*------------------------- 64 bit atomic operations -------------------------*/
 
 static inline int
@@ -421,7 +418,6 @@ static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
 {
        return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
 }
-
 /**
  * Atomically set a 64-bit counter to 0.
  *
@@ -432,6 +428,13 @@ static inline void rte_atomic64_clear(rte_atomic64_t *v)
 {
        v->cnt = 0;
 }
+
+static inline uint64_t
+rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
+{
+       return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
+}
+
 #endif
 
 #ifdef __cplusplus