#ifdef __DOXYGEN__
+/** @name Memory Barrier
+ */
+///@{
/**
* General memory barrier.
*
* This function is architecture dependent.
*/
static inline void rte_rmb(void);
+///@}
+/** @name SMP Memory Barrier
+ */
+///@{
/**
* General memory barrier between lcores
*
* Guarantees that the LOAD and STORE operations that precede the
* rte_smp_mb() call are globally visible across the lcores
- * before the the LOAD and STORE operations that follows it.
+ * before the LOAD and STORE operations that follows it.
*/
static inline void rte_smp_mb(void);
*
* Guarantees that the STORE operations that precede the
* rte_smp_wmb() call are globally visible across the lcores
- * before the the STORE operations that follows it.
+ * before the STORE operations that follows it.
*/
static inline void rte_smp_wmb(void);
*
* Guarantees that the LOAD operations that precede the
* rte_smp_rmb() call are globally visible across the lcores
- * before the the LOAD operations that follows it.
+ * before the LOAD operations that follows it.
*/
static inline void rte_smp_rmb(void);
+///@}
+/** @name I/O Memory Barrier
+ */
+///@{
/**
* General memory barrier for I/O device
*
* operations that follow it.
*/
static inline void rte_io_rmb(void);
+///@}
+
+/** @name Coherent I/O Memory Barrier
+ *
+ * Coherent I/O memory barrier is a lightweight version of I/O memory
+ * barriers which are system-wide data synchronization barriers. This
+ * is for only coherent memory domain between lcore and I/O device but
+ * it is same as the I/O memory barriers in most of architectures.
+ * However, some architecture provides even lighter barriers which are
+ * somewhere in between I/O memory barriers and SMP memory barriers.
+ * For example, in case of ARMv8, DMB(data memory barrier) instruction
+ * can have different shareability domains - inner-shareable and
+ * outer-shareable. And inner-shareable DMB fits for SMP memory
+ * barriers and outer-shareable DMB for coherent I/O memory barriers,
+ * which acts on coherent memory.
+ *
+ * In most cases, I/O memory barriers are safer but if operations are
+ * on coherent memory instead of incoherent MMIO region of a device,
+ * then coherent I/O memory barriers can be used and this could bring
+ * performance gain depending on architectures.
+ */
+///@{
+/**
+ * Write memory barrier for coherent memory between lcore and I/O device
+ *
+ * Guarantees that the STORE operations on coherent memory that
+ * precede the rte_cio_wmb() call are visible to I/O device before the
+ * STORE operations that follow it.
+ */
+static inline void rte_cio_wmb(void);
+
+/**
+ * Read memory barrier for coherent memory between lcore and I/O device
+ *
+ * Guarantees that the LOAD operations on coherent memory updated by
+ * I/O device that precede the rte_cio_rmb() call are visible to CPU
+ * before the LOAD operations that follow it.
+ */
+static inline void rte_cio_rmb(void);
+///@}
#endif /* __DOXYGEN__ */