eal: add new prefetch write variants

[dpdk.git] / lib / librte_eal / include / generic / rte_prefetch.h

diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h
index 6e47bdf..df9764e 100644 (file)
--- a/lib/librte_eal/include/generic/rte_prefetch.h
+++ b/lib/librte_eal/include/generic/rte_prefetch.h
@@ -5,6 +5,8 @@
 #ifndef _RTE_PREFETCH_H_
 #define _RTE_PREFETCH_H_
 
+#include <rte_compat.h>
+
 /**
  * @file
  *
@@ -51,4 +53,67 @@ static inline void rte_prefetch2(const volatile void *p);
  */
 static inline void rte_prefetch_non_temporal(const volatile void *p);
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
+ *
+ * Prefetch a cache line into all cache levels, with intention to write. This
+ * prefetch variant hints to the CPU that the program is expecting to write to
+ * the cache line being prefetched.
+ *
+ * @param p Address to prefetch
+ */
+__rte_experimental
+static inline void
+rte_prefetch0_write(const void *p)
+{
+       /* 1 indicates intention to write, 3 sets target cache level to L1. See
+        * GCC docs where these integer constants are described in more detail:
+        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
+        */
+       __builtin_prefetch(p, 1, 3);
+}
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
+ *
+ * Prefetch a cache line into all cache levels, except the 0th, with intention
+ * to write. This prefetch variant hints to the CPU that the program is
+ * expecting to write to the cache line being prefetched.
+ *
+ * @param p Address to prefetch
+ */
+__rte_experimental
+static inline void
+rte_prefetch1_write(const void *p)
+{
+       /* 1 indicates intention to write, 2 sets target cache level to L2. See
+        * GCC docs where these integer constants are described in more detail:
+        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
+        */
+       __builtin_prefetch(p, 1, 2);
+}
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
+ *
+ * Prefetch a cache line into all cache levels, except the 0th and 1st, with
+ * intention to write. This prefetch variant hints to the CPU that the program
+ * is expecting to write to the cache line being prefetched.
+ *
+ * @param p Address to prefetch
+ */
+__rte_experimental
+static inline void
+rte_prefetch2_write(const void *p)
+{
+       /* 1 indicates intention to write, 1 sets target cache level to L3. See
+        * GCC docs where these integer constants are described in more detail:
+        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
+        */
+       __builtin_prefetch(p, 1, 1);
+}
+
 #endif /* _RTE_PREFETCH_H_ */