/*-
* GPL LICENSE SUMMARY
*
- * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
+ * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
};
-static const enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
+static char *intr_mode = NULL;
+static enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
/* PCI device id table */
static struct pci_device_id igbuio_pci_ids[] = {
unsigned long addr, len;
void *internal_addr;
+ if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
+ return (EINVAL);
+
addr = pci_resource_start(dev, pci_bar);
len = pci_resource_len(dev, pci_bar);
if (addr == 0 || len == 0)
return 0;
}
+/* Get pci port io resources described by bar #pci_bar in uio resource n. */
+static int
+igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
+ int n, int pci_bar, const char *name)
+{
+ unsigned long addr, len;
+
+ if (sizeof(info->port) / sizeof (info->port[0]) <= n)
+ return (EINVAL);
+
+ addr = pci_resource_start(dev, pci_bar);
+ len = pci_resource_len(dev, pci_bar);
+ if (addr == 0 || len == 0)
+ return (-1);
+
+ info->port[n].name = name;
+ info->port[n].start = addr;
+ info->port[n].size = len;
+ info->port[n].porttype = UIO_PORT_X86;
+
+ return (0);
+}
+
/* Unmap previously ioremap'd resources */
static void
igbuio_pci_release_iomem(struct uio_info *info)
}
}
+static int
+igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
+{
+ int i, iom, iop, ret;
+ unsigned long flags;
+ static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
+ "BAR0",
+ "BAR1",
+ "BAR2",
+ "BAR3",
+ "BAR4",
+ "BAR5",
+ };
+
+ iom = 0;
+ iop = 0;
+
+ for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
+ if (pci_resource_len(dev, i) != 0 &&
+ pci_resource_start(dev, i) != 0) {
+ flags = pci_resource_flags(dev, i);
+ if (flags & IORESOURCE_MEM) {
+ if ((ret = igbuio_pci_setup_iomem(dev, info,
+ iom, i, bar_names[i])) != 0)
+ return (ret);
+ iom++;
+ } else if (flags & IORESOURCE_IO) {
+ if ((ret = igbuio_pci_setup_ioport(dev, info,
+ iop, i, bar_names[i])) != 0)
+ return (ret);
+ iop++;
+ }
+ }
+ }
+
+ return ((iom != 0) ? ret : ENOENT);
+}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
static int __devinit
+#else
+static int
+#endif
igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct rte_uio_pci_dev *udev;
goto fail_free;
}
- /* XXX should we use 64 bits ? */
- /* set 32-bit DMA mask */
- if (pci_set_dma_mask(dev,(uint64_t)0xffffffff)) {
- printk(KERN_ERR "Cannot set DMA mask\n");
- goto fail_disable;
- }
-
/*
* reserve device's PCI memory regions for use by this
* module
pci_set_master(dev);
/* remap IO memory */
- if (igbuio_pci_setup_iomem(dev, &udev->info, 0, 0, "config"))
- goto fail_release_regions;
+ if (igbuio_setup_bars(dev, &udev->info))
+ goto fail_release_iomem;
+
+ /* set 64-bit DMA mask */
+ if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
+ printk(KERN_ERR "Cannot set DMA mask\n");
+ goto fail_release_iomem;
+ } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
+ printk(KERN_ERR "Cannot set consistent DMA mask\n");
+ goto fail_release_iomem;
+ }
/* fill uio infos */
udev->info.name = "Intel IGB UIO";
igbuio_pci_release_iomem(&udev->info);
if (udev->mode == IGBUIO_MSIX_INTR_MODE)
pci_disable_msix(udev->pdev);
-fail_release_regions:
pci_release_regions(dev);
fail_disable:
pci_disable_device(dev);
uio_unregister_device(info);
igbuio_pci_release_iomem(info);
- if (((struct rte_uio_pci_dev *)info->priv)->mode == IGBUIO_MSIX_INTR_MODE)
+ if (((struct rte_uio_pci_dev *)info->priv)->mode ==
+ IGBUIO_MSIX_INTR_MODE)
pci_disable_msix(dev);
pci_release_regions(dev);
pci_disable_device(dev);
kfree(info);
}
+static int
+igbuio_config_intr_mode(char *intr_str)
+{
+ if (!intr_str) {
+ printk(KERN_INFO "Use MSIX interrupt by default\n");
+ return 0;
+ }
+
+ if (!strcmp(intr_str, "msix")) {
+ igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
+ printk(KERN_INFO "Use MSIX interrupt\n");
+ } else if (!strcmp(intr_str, "legacy")) {
+ igbuio_intr_mode_preferred = IGBUIO_LEGACY_INTR_MODE;
+ printk(KERN_INFO "Use legacy interrupt\n");
+ } else {
+ printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static struct pci_driver igbuio_pci_driver = {
.name = "igb_uio",
.id_table = igbuio_pci_ids,
static int __init
igbuio_pci_init_module(void)
{
+ int ret;
+
+ ret = igbuio_config_intr_mode(intr_mode);
+ if (ret < 0)
+ return ret;
+
return pci_register_driver(&igbuio_pci_driver);
}
module_init(igbuio_pci_init_module);
module_exit(igbuio_pci_exit_module);
+module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(intr_mode,
+"igb_uio interrupt mode (default=msix):\n"
+" msix Use MSIX interrupt\n"
+" legacy Use Legacy interrupt\n"
+"\n");
+
MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Intel Corporation");