/*-
* GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
+ *
+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
+ * The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
- *
+ *
* Contact Information:
* Intel Corporation
- *
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/version.h>
-/**
- * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
- * but none of them in kernel 2.6.35.
- */
-#ifndef PCI_MSIX_ENTRY_SIZE
-#define PCI_MSIX_ENTRY_SIZE 16
-#define PCI_MSIX_ENTRY_LOWER_ADDR 0
-#define PCI_MSIX_ENTRY_UPPER_ADDR 4
-#define PCI_MSIX_ENTRY_DATA 8
-#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
-#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
+#ifdef CONFIG_XEN_DOM0
+#include <xen/xen.h>
+#endif
+#include <rte_pci_dev_features.h>
+
+#ifdef RTE_PCI_CONFIG
+#define PCI_SYS_FILE_BUF_SIZE 10
+#define PCI_DEV_CAP_REG 0xA4
+#define PCI_DEV_CTRL_REG 0xA8
+#define PCI_DEV_CAP_EXT_TAG_MASK 0x20
+#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
+#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
#endif
-
-#define IGBUIO_NUM_MSI_VECTORS 1
-
-/* interrupt mode */
-enum igbuio_intr_mode {
- IGBUIO_LEGACY_INTR_MODE = 0,
- IGBUIO_MSI_INTR_MODE,
- IGBUIO_MSIX_INTR_MODE,
- IGBUIO_INTR_MODE_MAX
-};
/**
* A structure describing the private information for a uio device.
struct rte_uio_pci_dev {
struct uio_info info;
struct pci_dev *pdev;
- spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
- enum igbuio_intr_mode mode;
- struct msix_entry \
- msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
+ enum rte_intr_mode mode;
};
static char *intr_mode = NULL;
-static enum igbuio_intr_mode igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
-
-/* PCI device id table */
-static struct pci_device_id igbuio_pci_ids[] = {
-#define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {PCI_DEVICE(vend, dev)},
-#define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {PCI_DEVICE(vend, dev)},
-#define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {PCI_DEVICE(vend, dev)},
-#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {PCI_DEVICE(vend, dev)},
-#define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {PCI_DEVICE(vend, dev)},
-#include <rte_pci_dev_ids.h>
-{ 0, },
-};
-
-MODULE_DEVICE_TABLE(pci, igbuio_pci_ids);
+static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
static inline struct rte_uio_pci_dev *
igbuio_get_uio_pci_dev(struct uio_info *info)
}
/* sriov sysfs */
-int local_pci_num_vf(struct pci_dev *dev)
-{
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34)
+static int pci_num_vf(struct pci_dev *dev)
struct iov {
int pos;
int nres;
u16 total;
u16 initial;
u16 nr_virtfn;
- } *iov = (struct iov*)dev->sriov;
+ } *iov = (struct iov *)dev->sriov;
if (!dev->is_physfn)
return 0;
-
+
return iov->nr_virtfn;
-#else
- return pci_num_vf(dev);
-#endif
}
+#endif
static ssize_t
show_max_vfs(struct device *dev, struct device_attribute *attr,
char *buf)
{
- return snprintf(buf, 10, "%u\n", local_pci_num_vf(
- container_of(dev, struct pci_dev, dev)));
+ return snprintf(buf, 10, "%u\n",
+ pci_num_vf(container_of(dev, struct pci_dev, dev)));
}
static ssize_t
if (0 == max_vfs)
pci_disable_sriov(pdev);
- else if (0 == local_pci_num_vf(pdev))
+ else if (0 == pci_num_vf(pdev))
err = pci_enable_sriov(pdev, max_vfs);
else /* do nothing if change max_vfs number */
err = -EINVAL;
- return err ? err : count;
+ return err ? err : count;
+}
+
+#ifdef RTE_PCI_CONFIG
+static ssize_t
+show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+ uint32_t val = 0;
+
+ pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
+ if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
+ return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
+
+ val = 0;
+ pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
+ PCI_DEV_CTRL_REG, &val);
+
+ return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
+ (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
+}
+
+static ssize_t
+store_extended_tag(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+ uint32_t val = 0, enable;
+
+ if (strncmp(buf, "on", 2) == 0)
+ enable = 1;
+ else if (strncmp(buf, "off", 3) == 0)
+ enable = 0;
+ else
+ return -EINVAL;
+
+ pci_cfg_access_lock(pci_dev);
+ pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
+ PCI_DEV_CAP_REG, &val);
+ if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
+ pci_cfg_access_unlock(pci_dev);
+ return -EPERM;
+ }
+
+ val = 0;
+ pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
+ PCI_DEV_CTRL_REG, &val);
+ if (enable)
+ val |= PCI_DEV_CTRL_EXT_TAG_MASK;
+ else
+ val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
+ pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
+ PCI_DEV_CTRL_REG, val);
+ pci_cfg_access_unlock(pci_dev);
+
+ return count;
+}
+
+static ssize_t
+show_max_read_request_size(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+ int val = pcie_get_readrq(pci_dev);
+
+ return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
}
+static ssize_t
+store_max_read_request_size(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
+ unsigned long size = 0;
+ int ret;
+
+ if (strict_strtoul(buf, 0, &size) != 0)
+ return -EINVAL;
+
+ ret = pcie_set_readrq(pci_dev, (int)size);
+ if (ret < 0)
+ return ret;
+
+ return count;
+}
+#endif
+
static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
+#ifdef RTE_PCI_CONFIG
+static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
+ store_extended_tag);
+static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
+ show_max_read_request_size, store_max_read_request_size);
+#endif
+
static struct attribute *dev_attrs[] = {
&dev_attr_max_vfs.attr,
- NULL,
+#ifdef RTE_PCI_CONFIG
+ &dev_attr_extended_tag.attr,
+ &dev_attr_max_read_request_size.attr,
+#endif
+ NULL,
};
static const struct attribute_group dev_attr_grp = {
.attrs = dev_attrs,
};
-static inline int
-pci_lock(struct pci_dev * pdev)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
+/* Check if INTX works to control irq's.
+ * Set's INTX_DISABLE flag and reads it back
+ */
+static bool pci_intx_mask_supported(struct pci_dev *dev)
{
- /* Some function names changes between 3.2.0 and 3.3.0... */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
- pci_block_user_cfg_access(pdev);
- return 1;
-#else
- return pci_cfg_access_trylock(pdev);
-#endif
+ bool mask_supported = false;
+ uint16_t orig, new
+
+ pci_block_user_cfg_access(dev);
+ pci_read_config_word(pdev, PCI_COMMAND, &orig);
+ pci_write_config_word(dev, PCI_COMMAND,
+ orig ^ PCI_COMMAND_INTX_DISABLE);
+ pci_read_config_word(dev, PCI_COMMAND, &new);
+
+ if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
+ dev_err(&dev->dev, "Command register changed from "
+ "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
+ } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
+ mask_supported = true;
+ pci_write_config_word(dev, PCI_COMMAND, orig);
+ }
+ pci_unblock_user_cfg_access(dev);
}
-static inline void
-pci_unlock(struct pci_dev * pdev)
+static bool pci_check_and_mask_intx(struct pci_dev *pdev)
{
- /* Some function names changes between 3.2.0 and 3.3.0... */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
- pci_unblock_user_cfg_access(pdev);
-#else
- pci_cfg_access_unlock(pdev);
-#endif
+ bool pending;
+ uint32_t status;
+
+ pci_block_user_cfg_access(dev);
+ pci_read_config_dword(pdev, PCI_COMMAND, &status);
+
+ /* interrupt is not ours, goes to out */
+ pending = (((status >> 16) & PCI_STATUS_INTERRUPT) != 0);
+ if (pending) {
+ uint16_t old, new;
+
+ old = status;
+ if (state != 0)
+ new = old & (~PCI_COMMAND_INTX_DISABLE);
+ else
+ new = old | PCI_COMMAND_INTX_DISABLE;
+
+ if (old != new)
+ pci_write_config_word(pdev, PCI_COMMAND, new);
+ }
+ pci_unblock_user_cfg_access(dev);
+
+ return pending;
}
+#endif
-/**
+/*
* It masks the msix on/off of generating MSI-X messages.
*/
-static int
+static void
igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
{
- uint32_t mask_bits = desc->masked;
+ u32 mask_bits = desc->masked;
unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_VECTOR_CTRL;
readl(desc->mask_base);
desc->masked = mask_bits;
}
-
- return 0;
-}
-
-/**
- * This function sets/clears the masks for generating LSC interrupts.
- *
- * @param info
- * The pointer to struct uio_info.
- * @param on
- * The on/off flag of masking LSC.
- * @return
- * -On success, zero value.
- * -On failure, a negative value.
- */
-static int
-igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
-{
- struct pci_dev *pdev = udev->pdev;
-
- if (udev->mode == IGBUIO_MSIX_INTR_MODE) {
- struct msi_desc *desc;
-
- list_for_each_entry(desc, &pdev->msi_list, list) {
- igbuio_msix_mask_irq(desc, state);
- }
- }
- else if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
- uint32_t status;
- uint16_t old, new;
-
- pci_read_config_dword(pdev, PCI_COMMAND, &status);
- old = status;
- if (state != 0)
- new = old & (~PCI_COMMAND_INTX_DISABLE);
- else
- new = old | PCI_COMMAND_INTX_DISABLE;
-
- if (old != new)
- pci_write_config_word(pdev, PCI_COMMAND, new);
- }
-
- return 0;
}
/**
static int
igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
{
- unsigned long flags;
struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
struct pci_dev *pdev = udev->pdev;
- spin_lock_irqsave(&udev->lock, flags);
- if (!pci_lock(pdev)) {
- spin_unlock_irqrestore(&udev->lock, flags);
- return -1;
- }
+ pci_cfg_access_lock(pdev);
+ if (udev->mode == RTE_INTR_MODE_LEGACY)
+ pci_intx(pdev, !!irq_state);
- igbuio_set_interrupt_mask(udev, irq_state);
+ else if (udev->mode == RTE_INTR_MODE_MSIX) {
+ struct msi_desc *desc;
- pci_unlock(pdev);
- spin_unlock_irqrestore(&udev->lock, flags);
+ list_for_each_entry(desc, &pdev->msi_list, list)
+ igbuio_msix_mask_irq(desc, irq_state);
+ }
+ pci_cfg_access_unlock(pdev);
return 0;
}
static irqreturn_t
igbuio_pci_irqhandler(int irq, struct uio_info *info)
{
- irqreturn_t ret = IRQ_NONE;
- unsigned long flags;
struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
- struct pci_dev *pdev = udev->pdev;
- uint32_t cmd_status_dword;
- uint16_t status;
-
- spin_lock_irqsave(&udev->lock, flags);
- /* block userspace PCI config reads/writes */
- if (!pci_lock(pdev))
- goto spin_unlock;
-
- /* for legacy mode, interrupt maybe shared */
- if (udev->mode == IGBUIO_LEGACY_INTR_MODE) {
- pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
- status = cmd_status_dword >> 16;
- /* interrupt is not ours, goes to out */
- if (!(status & PCI_STATUS_INTERRUPT))
- goto done;
- }
- igbuio_set_interrupt_mask(udev, 0);
- ret = IRQ_HANDLED;
-done:
- /* unblock userspace PCI config reads/writes */
- pci_unlock(pdev);
-spin_unlock:
- spin_unlock_irqrestore(&udev->lock, flags);
- printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
+ /* Legacy mode need to mask in hardware */
+ if (udev->mode == RTE_INTR_MODE_LEGACY &&
+ !pci_check_and_mask_intx(udev->pdev))
+ return IRQ_NONE;
+
+ /* Message signal mode, no share IRQ and automasked */
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_XEN_DOM0
+static int
+igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
+{
+ int idx;
+
+ idx = (int)vma->vm_pgoff;
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+ vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
- return ret;
+ return remap_pfn_range(vma,
+ vma->vm_start,
+ info->mem[idx].addr >> PAGE_SHIFT,
+ vma->vm_end - vma->vm_start,
+ vma->vm_page_prot);
}
+/**
+ * This is uio device mmap method which will use igbuio mmap for Xen
+ * Dom0 environment.
+ */
+static int
+igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
+{
+ int idx;
+
+ if (vma->vm_pgoff >= MAX_UIO_MAPS)
+ return -EINVAL;
+
+ if (info->mem[vma->vm_pgoff].size == 0)
+ return -EINVAL;
+
+ idx = (int)vma->vm_pgoff;
+ switch (info->mem[idx].memtype) {
+ case UIO_MEM_PHYS:
+ return igbuio_dom0_mmap_phys(info, vma);
+ case UIO_MEM_LOGICAL:
+ case UIO_MEM_VIRTUAL:
+ default:
+ return -EINVAL;
+ }
+}
+#endif
+
/* Remap pci resources described by bar #pci_bar in uio resource n. */
static int
igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
unsigned long addr, len;
void *internal_addr;
- if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
- return (EINVAL);
+ if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
+ return -EINVAL;
addr = pci_resource_start(dev, pci_bar);
len = pci_resource_len(dev, pci_bar);
{
unsigned long addr, len;
- if (sizeof(info->port) / sizeof (info->port[0]) <= n)
- return (EINVAL);
+ if (sizeof(info->port) / sizeof(info->port[0]) <= n)
+ return -EINVAL;
addr = pci_resource_start(dev, pci_bar);
len = pci_resource_len(dev, pci_bar);
if (addr == 0 || len == 0)
- return (-1);
+ return -EINVAL;
info->port[n].name = name;
info->port[n].start = addr;
info->port[n].size = len;
info->port[n].porttype = UIO_PORT_X86;
- return (0);
+ return 0;
}
/* Unmap previously ioremap'd resources */
igbuio_pci_release_iomem(struct uio_info *info)
{
int i;
+
for (i = 0; i < MAX_UIO_MAPS; i++) {
if (info->mem[i].internal_addr)
iounmap(info->mem[i].internal_addr);
pci_resource_start(dev, i) != 0) {
flags = pci_resource_flags(dev, i);
if (flags & IORESOURCE_MEM) {
- if ((ret = igbuio_pci_setup_iomem(dev, info,
- iom, i, bar_names[i])) != 0)
- return (ret);
+ ret = igbuio_pci_setup_iomem(dev, info, iom,
+ i, bar_names[i]);
+ if (ret != 0)
+ return ret;
iom++;
} else if (flags & IORESOURCE_IO) {
- if ((ret = igbuio_pci_setup_ioport(dev, info,
- iop, i, bar_names[i])) != 0)
- return (ret);
+ ret = igbuio_pci_setup_ioport(dev, info, iop,
+ i, bar_names[i]);
+ if (ret != 0)
+ return ret;
iop++;
}
}
}
- return ((iom != 0) ? ret : ENOENT);
+ return (iom != 0) ? ret : -ENOENT;
}
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
static int __devinit
#else
static int
igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct rte_uio_pci_dev *udev;
+ struct msix_entry msix_entry;
+ int err;
udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
if (!udev)
* enable device: ask low-level code to enable I/O and
* memory
*/
- if (pci_enable_device(dev)) {
- printk(KERN_ERR "Cannot enable PCI device\n");
+ err = pci_enable_device(dev);
+ if (err != 0) {
+ dev_err(&dev->dev, "Cannot enable PCI device\n");
goto fail_free;
}
* reserve device's PCI memory regions for use by this
* module
*/
- if (pci_request_regions(dev, "igb_uio")) {
- printk(KERN_ERR "Cannot request regions\n");
+ err = pci_request_regions(dev, "igb_uio");
+ if (err != 0) {
+ dev_err(&dev->dev, "Cannot request regions\n");
goto fail_disable;
}
pci_set_master(dev);
/* remap IO memory */
- if (igbuio_setup_bars(dev, &udev->info))
+ err = igbuio_setup_bars(dev, &udev->info);
+ if (err != 0)
goto fail_release_iomem;
/* set 64-bit DMA mask */
- if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
- printk(KERN_ERR "Cannot set DMA mask\n");
+ err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
+ if (err != 0) {
+ dev_err(&dev->dev, "Cannot set DMA mask\n");
goto fail_release_iomem;
- } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
- printk(KERN_ERR "Cannot set consistent DMA mask\n");
+ }
+
+ err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
+ if (err != 0) {
+ dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
goto fail_release_iomem;
}
/* fill uio infos */
- udev->info.name = "Intel IGB UIO";
+ udev->info.name = "igb_uio";
udev->info.version = "0.1";
udev->info.handler = igbuio_pci_irqhandler;
udev->info.irqcontrol = igbuio_pci_irqcontrol;
+ udev->info.irq = dev->irq;
+#ifdef CONFIG_XEN_DOM0
+ /* check if the driver run on Xen Dom0 */
+ if (xen_initial_domain())
+ udev->info.mmap = igbuio_dom0_pci_mmap;
+#endif
udev->info.priv = udev;
udev->pdev = dev;
- udev->mode = 0; /* set the default value for interrupt mode */
- spin_lock_init(&udev->lock);
-
- /* check if it need to try msix first */
- if (igbuio_intr_mode_preferred == IGBUIO_MSIX_INTR_MODE) {
- int vector;
-
- for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
- udev->msix_entries[vector].entry = vector;
- if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
- udev->mode = IGBUIO_MSIX_INTR_MODE;
+ switch (igbuio_intr_mode_preferred) {
+ case RTE_INTR_MODE_NONE:
+ udev->info.irq = 0;
+ break;
+ case RTE_INTR_MODE_MSIX:
+ /* Only 1 msi-x vector needed */
+ msix_entry.entry = 0;
+ if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
+ dev_dbg(&dev->dev, "using MSI-X");
+ udev->info.irq = msix_entry.vector;
+ udev->mode = RTE_INTR_MODE_MSIX;
+ break;
}
- else {
- pci_disable_msix(udev->pdev);
- printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
+ /* fall back to INTX */
+ case RTE_INTR_MODE_LEGACY:
+ if (pci_intx_mask_supported(dev)) {
+ dev_dbg(&dev->dev, "using INTX");
+ udev->info.irq_flags = IRQF_SHARED;
+ udev->mode = RTE_INTR_MODE_LEGACY;
+ } else {
+ dev_err(&dev->dev, "PCI INTX mask not supported\n");
+ err = -EIO;
+ goto fail_release_iomem;
}
- }
- switch (udev->mode) {
- case IGBUIO_MSIX_INTR_MODE:
- udev->info.irq_flags = 0;
- udev->info.irq = udev->msix_entries[0].vector;
- break;
- case IGBUIO_MSI_INTR_MODE:
- break;
- case IGBUIO_LEGACY_INTR_MODE:
- udev->info.irq_flags = IRQF_SHARED;
- udev->info.irq = dev->irq;
break;
default:
- break;
+ dev_err(&dev->dev, "invalid IRQ mode %u",
+ igbuio_intr_mode_preferred);
+ err = -EINVAL;
+ goto fail_release_iomem;
}
- pci_set_drvdata(dev, udev);
- igbuio_pci_irqcontrol(&udev->info, 0);
-
- if (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))
+ err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
+ if (err != 0)
goto fail_release_iomem;
/* register uio driver */
- if (uio_register_device(&dev->dev, &udev->info))
- goto fail_release_iomem;
+ err = uio_register_device(&dev->dev, &udev->info);
+ if (err != 0)
+ goto fail_remove_group;
- printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
+ pci_set_drvdata(dev, udev);
+
+ dev_info(&dev->dev, "uio device registered with irq %lx\n",
+ udev->info.irq);
return 0;
-fail_release_iomem:
+fail_remove_group:
sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
+fail_release_iomem:
igbuio_pci_release_iomem(&udev->info);
- if (udev->mode == IGBUIO_MSIX_INTR_MODE)
+ if (udev->mode == RTE_INTR_MODE_MSIX)
pci_disable_msix(udev->pdev);
pci_release_regions(dev);
fail_disable:
fail_free:
kfree(udev);
- return -ENODEV;
+ return err;
}
static void
igbuio_pci_remove(struct pci_dev *dev)
{
struct uio_info *info = pci_get_drvdata(dev);
+ struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
if (info->priv == NULL) {
- printk(KERN_DEBUG "Not igbuio device\n");
+ pr_notice("Not igbuio device\n");
return;
}
sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
uio_unregister_device(info);
igbuio_pci_release_iomem(info);
- if (((struct rte_uio_pci_dev *)info->priv)->mode ==
- IGBUIO_MSIX_INTR_MODE)
+ if (udev->mode == RTE_INTR_MODE_MSIX)
pci_disable_msix(dev);
pci_release_regions(dev);
pci_disable_device(dev);
igbuio_config_intr_mode(char *intr_str)
{
if (!intr_str) {
- printk(KERN_INFO "Use MSIX interrupt by default\n");
+ pr_info("Use MSIX interrupt by default\n");
return 0;
}
- if (!strcmp(intr_str, "msix")) {
- igbuio_intr_mode_preferred = IGBUIO_MSIX_INTR_MODE;
- printk(KERN_INFO "Use MSIX interrupt\n");
- } else if (!strcmp(intr_str, "legacy")) {
- igbuio_intr_mode_preferred = IGBUIO_LEGACY_INTR_MODE;
- printk(KERN_INFO "Use legacy interrupt\n");
+ if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
+ igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
+ pr_info("Use MSIX interrupt\n");
+ } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
+ igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
+ pr_info("Use legacy interrupt\n");
} else {
- printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
+ pr_info("Error: bad parameter - %s\n", intr_str);
return -EINVAL;
}
static struct pci_driver igbuio_pci_driver = {
.name = "igb_uio",
- .id_table = igbuio_pci_ids,
+ .id_table = NULL,
.probe = igbuio_pci_probe,
.remove = igbuio_pci_remove,
};
module_init(igbuio_pci_init_module);
module_exit(igbuio_pci_exit_module);
-module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
+module_param(intr_mode, charp, S_IRUGO);
MODULE_PARM_DESC(intr_mode,
"igb_uio interrupt mode (default=msix):\n"
-" msix Use MSIX interrupt\n"
-" legacy Use Legacy interrupt\n"
+" " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
+" " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
"\n");
MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
git.droids-corp.org / dpdk.git / blobdiff