#include <rte_string_fns.h>
#include <rte_kvargs.h>
#include <rte_class.h>
+#include <rte_ether.h>
-#include "rte_ether.h"
#include "rte_ethdev.h"
#include "rte_ethdev_driver.h"
#include "ethdev_profile.h"
RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC),
RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM),
RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
+ RTE_RX_OFFLOAD_BIT2STR(RSS_HASH),
};
#undef RTE_RX_OFFLOAD_BIT2STR
RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO),
RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO),
RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
- RTE_TX_OFFLOAD_BIT2STR(MATCH_METADATA),
};
#undef RTE_TX_OFFLOAD_BIT2STR
-static const struct {
- uint64_t option;
- const char *name;
-} rte_burst_option_names[] = {
- { RTE_ETH_BURST_SCALAR, "Scalar" },
- { RTE_ETH_BURST_VECTOR, "Vector" },
-
- { RTE_ETH_BURST_ALTIVEC, "AltiVec" },
- { RTE_ETH_BURST_NEON, "Neon" },
- { RTE_ETH_BURST_SSE, "SSE" },
- { RTE_ETH_BURST_AVX2, "AVX2" },
- { RTE_ETH_BURST_AVX512, "AVX512" },
-
- { RTE_ETH_BURST_SCATTERED, "Scattered" },
- { RTE_ETH_BURST_BULK_ALLOC, "Bulk Alloc" },
- { RTE_ETH_BURST_SIMPLE, "Simple" },
- { RTE_ETH_BURST_PER_QUEUE, "Per Queue" },
-};
-
/**
* The user application callback description.
*
return rte_eth_devices[port_id].security_ctx;
}
-uint16_t
-rte_eth_dev_count(void)
-{
- return rte_eth_dev_count_avail();
-}
-
uint16_t
rte_eth_dev_count_avail(void)
{
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP);
+ if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
+ RTE_ETHDEV_LOG(INFO,
+ "Can't start Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
+ rx_queue_id, port_id);
+ return -EINVAL;
+ }
+
if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
RTE_ETHDEV_LOG(INFO,
"Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP);
+ if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) {
+ RTE_ETHDEV_LOG(INFO,
+ "Can't stop Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
+ rx_queue_id, port_id);
+ return -EINVAL;
+ }
+
if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
RTE_ETHDEV_LOG(INFO,
"Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP);
+ if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
+ RTE_ETHDEV_LOG(INFO,
+ "Can't start Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
+ tx_queue_id, port_id);
+ return -EINVAL;
+ }
+
if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
RTE_ETHDEV_LOG(INFO,
"Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP);
+ if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) {
+ RTE_ETHDEV_LOG(INFO,
+ "Can't stop Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n",
+ tx_queue_id, port_id);
+ return -EINVAL;
+ }
+
if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
RTE_ETHDEV_LOG(INFO,
"Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
goto rollback;
}
+ /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */
+ if (((dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) &&
+ (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_RSS_HASH)) {
+ RTE_ETHDEV_LOG(ERR,
+ "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested",
+ port_id,
+ rte_eth_dev_rx_offload_name(DEV_RX_OFFLOAD_RSS_HASH));
+ ret = -EINVAL;
+ goto rollback;
+ }
+
/*
* Setup new number of RX/TX queues and reconfigure device.
*/
return eth_err(port_id, ret);
}
+int
+rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
+ uint16_t nb_rx_desc,
+ const struct rte_eth_hairpin_conf *conf)
+{
+ int ret;
+ struct rte_eth_dev *dev;
+ struct rte_eth_hairpin_cap cap;
+ void **rxq;
+ int i;
+ int count;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
+
+ dev = &rte_eth_devices[port_id];
+ if (rx_queue_id >= dev->data->nb_rx_queues) {
+ RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
+ return -EINVAL;
+ }
+ ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
+ if (ret != 0)
+ return ret;
+ RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_hairpin_queue_setup,
+ -ENOTSUP);
+ /* if nb_rx_desc is zero use max number of desc from the driver. */
+ if (nb_rx_desc == 0)
+ nb_rx_desc = cap.max_nb_desc;
+ if (nb_rx_desc > cap.max_nb_desc) {
+ RTE_ETHDEV_LOG(ERR,
+ "Invalid value for nb_rx_desc(=%hu), should be: <= %hu",
+ nb_rx_desc, cap.max_nb_desc);
+ return -EINVAL;
+ }
+ if (conf->peer_count > cap.max_rx_2_tx) {
+ RTE_ETHDEV_LOG(ERR,
+ "Invalid value for number of peers for Rx queue(=%hu), should be: <= %hu",
+ conf->peer_count, cap.max_rx_2_tx);
+ return -EINVAL;
+ }
+ if (conf->peer_count == 0) {
+ RTE_ETHDEV_LOG(ERR,
+ "Invalid value for number of peers for Rx queue(=%hu), should be: > 0",
+ conf->peer_count);
+ return -EINVAL;
+ }
+ for (i = 0, count = 0; i < dev->data->nb_rx_queues &&
+ cap.max_nb_queues != UINT16_MAX; i++) {
+ if (i == rx_queue_id || rte_eth_dev_is_rx_hairpin_queue(dev, i))
+ count++;
+ }
+ if (count > cap.max_nb_queues) {
+ RTE_ETHDEV_LOG(ERR, "To many Rx hairpin queues max is %d",
+ cap.max_nb_queues);
+ return -EINVAL;
+ }
+ if (dev->data->dev_started)
+ return -EBUSY;
+ rxq = dev->data->rx_queues;
+ if (rxq[rx_queue_id] != NULL) {
+ RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
+ -ENOTSUP);
+ (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
+ rxq[rx_queue_id] = NULL;
+ }
+ ret = (*dev->dev_ops->rx_hairpin_queue_setup)(dev, rx_queue_id,
+ nb_rx_desc, conf);
+ if (ret == 0)
+ dev->data->rx_queue_state[rx_queue_id] =
+ RTE_ETH_QUEUE_STATE_HAIRPIN;
+ return eth_err(port_id, ret);
+}
+
int
rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
uint16_t nb_tx_desc, unsigned int socket_id,
tx_queue_id, nb_tx_desc, socket_id, &local_conf));
}
+int
+rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
+ uint16_t nb_tx_desc,
+ const struct rte_eth_hairpin_conf *conf)
+{
+ struct rte_eth_dev *dev;
+ struct rte_eth_hairpin_cap cap;
+ void **txq;
+ int i;
+ int count;
+ int ret;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
+ dev = &rte_eth_devices[port_id];
+ if (tx_queue_id >= dev->data->nb_tx_queues) {
+ RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
+ return -EINVAL;
+ }
+ ret = rte_eth_dev_hairpin_capability_get(port_id, &cap);
+ if (ret != 0)
+ return ret;
+ RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_hairpin_queue_setup,
+ -ENOTSUP);
+ /* if nb_rx_desc is zero use max number of desc from the driver. */
+ if (nb_tx_desc == 0)
+ nb_tx_desc = cap.max_nb_desc;
+ if (nb_tx_desc > cap.max_nb_desc) {
+ RTE_ETHDEV_LOG(ERR,
+ "Invalid value for nb_tx_desc(=%hu), should be: <= %hu",
+ nb_tx_desc, cap.max_nb_desc);
+ return -EINVAL;
+ }
+ if (conf->peer_count > cap.max_tx_2_rx) {
+ RTE_ETHDEV_LOG(ERR,
+ "Invalid value for number of peers for Tx queue(=%hu), should be: <= %hu",
+ conf->peer_count, cap.max_tx_2_rx);
+ return -EINVAL;
+ }
+ if (conf->peer_count == 0) {
+ RTE_ETHDEV_LOG(ERR,
+ "Invalid value for number of peers for Tx queue(=%hu), should be: > 0",
+ conf->peer_count);
+ return -EINVAL;
+ }
+ for (i = 0, count = 0; i < dev->data->nb_tx_queues &&
+ cap.max_nb_queues != UINT16_MAX; i++) {
+ if (i == tx_queue_id || rte_eth_dev_is_tx_hairpin_queue(dev, i))
+ count++;
+ }
+ if (count > cap.max_nb_queues) {
+ RTE_ETHDEV_LOG(ERR, "To many Tx hairpin queues max is %d",
+ cap.max_nb_queues);
+ return -EINVAL;
+ }
+ if (dev->data->dev_started)
+ return -EBUSY;
+ txq = dev->data->tx_queues;
+ if (txq[tx_queue_id] != NULL) {
+ RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
+ -ENOTSUP);
+ (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
+ txq[tx_queue_id] = NULL;
+ }
+ ret = (*dev->dev_ops->tx_hairpin_queue_setup)
+ (dev, tx_queue_id, nb_tx_desc, conf);
+ if (ret == 0)
+ dev->data->tx_queue_state[tx_queue_id] =
+ RTE_ETH_QUEUE_STATE_HAIRPIN;
+ return eth_err(port_id, ret);
+}
+
void
rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent,
void *userdata __rte_unused)
RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
dev = &rte_eth_devices[port_id];
+ if (dev->data->promiscuous == 1)
+ return 0;
+
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_enable, -ENOTSUP);
- if (dev->data->promiscuous == 0) {
- diag = (*dev->dev_ops->promiscuous_enable)(dev);
- dev->data->promiscuous = (diag == 0) ? 1 : 0;
- }
+ diag = (*dev->dev_ops->promiscuous_enable)(dev);
+ dev->data->promiscuous = (diag == 0) ? 1 : 0;
return eth_err(port_id, diag);
}
RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
dev = &rte_eth_devices[port_id];
+ if (dev->data->promiscuous == 0)
+ return 0;
+
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_disable, -ENOTSUP);
- if (dev->data->promiscuous == 1) {
- dev->data->promiscuous = 0;
- diag = (*dev->dev_ops->promiscuous_disable)(dev);
- if (diag != 0)
- dev->data->promiscuous = 1;
- }
+ dev->data->promiscuous = 0;
+ diag = (*dev->dev_ops->promiscuous_disable)(dev);
+ if (diag != 0)
+ dev->data->promiscuous = 1;
return eth_err(port_id, diag);
}
return j;
}
+int
+rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask,
+ uint32_t *set_ptypes, unsigned int num)
+{
+ const uint32_t valid_ptype_masks[] = {
+ RTE_PTYPE_L2_MASK,
+ RTE_PTYPE_L3_MASK,
+ RTE_PTYPE_L4_MASK,
+ RTE_PTYPE_TUNNEL_MASK,
+ RTE_PTYPE_INNER_L2_MASK,
+ RTE_PTYPE_INNER_L3_MASK,
+ RTE_PTYPE_INNER_L4_MASK,
+ };
+ const uint32_t *all_ptypes;
+ struct rte_eth_dev *dev;
+ uint32_t unused_mask;
+ unsigned int i, j;
+ int ret;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
+ dev = &rte_eth_devices[port_id];
+
+ if (num > 0 && set_ptypes == NULL)
+ return -EINVAL;
+
+ if (*dev->dev_ops->dev_supported_ptypes_get == NULL ||
+ *dev->dev_ops->dev_ptypes_set == NULL) {
+ ret = 0;
+ goto ptype_unknown;
+ }
+
+ if (ptype_mask == 0) {
+ ret = (*dev->dev_ops->dev_ptypes_set)(dev,
+ ptype_mask);
+ goto ptype_unknown;
+ }
+
+ unused_mask = ptype_mask;
+ for (i = 0; i < RTE_DIM(valid_ptype_masks); i++) {
+ uint32_t mask = ptype_mask & valid_ptype_masks[i];
+ if (mask && mask != valid_ptype_masks[i]) {
+ ret = -EINVAL;
+ goto ptype_unknown;
+ }
+ unused_mask &= ~valid_ptype_masks[i];
+ }
+
+ if (unused_mask) {
+ ret = -EINVAL;
+ goto ptype_unknown;
+ }
+
+ all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
+ if (all_ptypes == NULL) {
+ ret = 0;
+ goto ptype_unknown;
+ }
+
+ /*
+ * Accommodate as many set_ptypes as possible. If the supplied
+ * set_ptypes array is insufficient fill it partially.
+ */
+ for (i = 0, j = 0; set_ptypes != NULL &&
+ (all_ptypes[i] != RTE_PTYPE_UNKNOWN); ++i) {
+ if (ptype_mask & all_ptypes[i]) {
+ if (j < num - 1) {
+ set_ptypes[j] = all_ptypes[i];
+ j++;
+ continue;
+ }
+ break;
+ }
+ }
+
+ if (set_ptypes != NULL && j < num)
+ set_ptypes[j] = RTE_PTYPE_UNKNOWN;
+
+ return (*dev->dev_ops->dev_ptypes_set)(dev, ptype_mask);
+
+ptype_unknown:
+ if (num > 0)
+ set_ptypes[0] = RTE_PTYPE_UNKNOWN;
+
+ return ret;
+}
+
int
rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr)
{
return 0;
}
-
int
rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu)
{
rte_errno = ENOTSUP;
return NULL;
#endif
+ struct rte_eth_dev *dev;
+
/* check input parameters */
if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
rte_errno = EINVAL;
return NULL;
}
+ dev = &rte_eth_devices[port_id];
+ if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
+ rte_errno = EINVAL;
+ return NULL;
+ }
struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
if (cb == NULL) {
rte_errno = ENOTSUP;
return NULL;
#endif
+ struct rte_eth_dev *dev;
+
/* check input parameters */
if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) {
return NULL;
}
+ dev = &rte_eth_devices[port_id];
+ if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
+ rte_errno = EINVAL;
+ return NULL;
+ }
+
struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
if (cb == NULL) {
return -EINVAL;
}
+ if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) {
+ RTE_ETHDEV_LOG(INFO,
+ "Can't get hairpin Rx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
+ queue_id, port_id);
+ return -EINVAL;
+ }
+
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP);
memset(qinfo, 0, sizeof(*qinfo));
return -EINVAL;
}
+ if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) {
+ RTE_ETHDEV_LOG(INFO,
+ "Can't get hairpin Tx queue %"PRIu16" info of device with port_id=%"PRIu16"\n",
+ queue_id, port_id);
+ return -EINVAL;
+ }
+
RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP);
memset(qinfo, 0, sizeof(*qinfo));
dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode));
}
-const char *
-rte_eth_burst_mode_option_name(uint64_t option)
-{
- const char *name = "";
- unsigned int i;
-
- for (i = 0; i < RTE_DIM(rte_burst_option_names); ++i) {
- if (option == rte_burst_option_names[i].option) {
- name = rte_burst_option_names[i].name;
- break;
- }
- }
-
- return name;
-}
-
int
rte_eth_dev_set_mc_addr_list(uint16_t port_id,
struct rte_ether_addr *mc_addr_set,
return 0;
}
+int
+rte_eth_dev_hairpin_capability_get(uint16_t port_id,
+ struct rte_eth_hairpin_cap *cap)
+{
+ struct rte_eth_dev *dev;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
+
+ dev = &rte_eth_devices[port_id];
+ RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_cap_get, -ENOTSUP);
+ memset(cap, 0, sizeof(*cap));
+ return eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap));
+}
+
+int
+rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
+{
+ if (dev->data->rx_queue_state[queue_id] ==
+ RTE_ETH_QUEUE_STATE_HAIRPIN)
+ return 1;
+ return 0;
+}
+
+int
+rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id)
+{
+ if (dev->data->tx_queue_state[queue_id] ==
+ RTE_ETH_QUEUE_STATE_HAIRPIN)
+ return 1;
+ return 0;
+}
+
int
rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)
{