#include <rte_config.h>
#include <rte_ether.h>
+#include "rte_ethdev_trace_fp.h"
#include "rte_dev_info.h"
extern int rte_eth_dev_logtype;
#define ETH_LINK_SPEED_50G (1 << 12) /**< 50 Gbps */
#define ETH_LINK_SPEED_56G (1 << 13) /**< 56 Gbps */
#define ETH_LINK_SPEED_100G (1 << 14) /**< 100 Gbps */
+#define ETH_LINK_SPEED_200G (1 << 15) /**< 200 Gbps */
/**
* Ethernet numeric link speeds in Mbps
#define ETH_SPEED_NUM_50G 50000 /**< 50 Gbps */
#define ETH_SPEED_NUM_56G 56000 /**< 56 Gbps */
#define ETH_SPEED_NUM_100G 100000 /**< 100 Gbps */
+#define ETH_SPEED_NUM_200G 200000 /**< 200 Gbps */
/**
* A structure used to retrieve link-level information of an Ethernet port.
uint16_t link_duplex : 1; /**< ETH_LINK_[HALF/FULL]_DUPLEX */
uint16_t link_autoneg : 1; /**< ETH_LINK_[AUTONEG/FIXED] */
uint16_t link_status : 1; /**< ETH_LINK_[DOWN/UP] */
-} __attribute__((aligned(8))); /**< aligned for atomic64 read/write */
+} __rte_aligned(8); /**< aligned for atomic64 read/write */
/* Utility constants */
#define ETH_LINK_HALF_DUPLEX 0 /**< Half-duplex connection (see link_duplex). */
/** The multi-queue packet distribution mode to be used, e.g. RSS. */
enum rte_eth_rx_mq_mode mq_mode;
uint32_t max_rx_pkt_len; /**< Only used if JUMBO_FRAME enabled. */
+ /** Maximum allowed size of LRO aggregated packet. */
+ uint32_t max_lro_pkt_size;
uint16_t split_hdr_size; /**< hdr buf size (header_split enabled).*/
/**
* Per-port Rx offloads to be set using DEV_RX_OFFLOAD_* flags.
* structure are allowed to be set.
*/
uint64_t offloads;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
#define ETH_RSS_GENEVE (1ULL << 20)
#define ETH_RSS_NVGRE (1ULL << 21)
#define ETH_RSS_GTPU (1ULL << 23)
+#define ETH_RSS_ETH (1ULL << 24)
+#define ETH_RSS_S_VLAN (1ULL << 25)
+#define ETH_RSS_C_VLAN (1ULL << 26)
+#define ETH_RSS_ESP (1ULL << 27)
+#define ETH_RSS_AH (1ULL << 28)
+#define ETH_RSS_L2TPV3 (1ULL << 29)
+#define ETH_RSS_PFCP (1ULL << 30)
+#define ETH_RSS_PPPOE (1ULL << 31)
/*
* We use the following macros to combine with above ETH_RSS_* for
#define ETH_RSS_L3_DST_ONLY (1ULL << 62)
#define ETH_RSS_L4_SRC_ONLY (1ULL << 61)
#define ETH_RSS_L4_DST_ONLY (1ULL << 60)
+#define ETH_RSS_L2_SRC_ONLY (1ULL << 59)
+#define ETH_RSS_L2_DST_ONLY (1ULL << 58)
+
+/*
+ * Only select IPV6 address prefix as RSS input set according to
+ * https://tools.ietf.org/html/rfc6052
+ * Must be combined with ETH_RSS_IPV6, ETH_RSS_NONFRAG_IPV6_UDP,
+ * ETH_RSS_NONFRAG_IPV6_TCP, ETH_RSS_NONFRAG_IPV6_SCTP.
+ */
+#define RTE_ETH_RSS_L3_PRE32 (1ULL << 57)
+#define RTE_ETH_RSS_L3_PRE40 (1ULL << 56)
+#define RTE_ETH_RSS_L3_PRE48 (1ULL << 55)
+#define RTE_ETH_RSS_L3_PRE56 (1ULL << 54)
+#define RTE_ETH_RSS_L3_PRE64 (1ULL << 53)
+#define RTE_ETH_RSS_L3_PRE96 (1ULL << 52)
/**
* For input set change of hash filter, if SRC_ONLY and DST_ONLY of
return rss_hf;
}
+#define ETH_RSS_IPV6_PRE32 ( \
+ ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_L3_PRE32)
+
+#define ETH_RSS_IPV6_PRE40 ( \
+ ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_L3_PRE40)
+
+#define ETH_RSS_IPV6_PRE48 ( \
+ ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_L3_PRE48)
+
+#define ETH_RSS_IPV6_PRE56 ( \
+ ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_L3_PRE56)
+
+#define ETH_RSS_IPV6_PRE64 ( \
+ ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_L3_PRE64)
+
+#define ETH_RSS_IPV6_PRE96 ( \
+ ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_L3_PRE96)
+
+#define ETH_RSS_IPV6_PRE32_UDP ( \
+ ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_L3_PRE32)
+
+#define ETH_RSS_IPV6_PRE40_UDP ( \
+ ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_L3_PRE40)
+
+#define ETH_RSS_IPV6_PRE48_UDP ( \
+ ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_L3_PRE48)
+
+#define ETH_RSS_IPV6_PRE56_UDP ( \
+ ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_L3_PRE56)
+
+#define ETH_RSS_IPV6_PRE64_UDP ( \
+ ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_L3_PRE64)
+
+#define ETH_RSS_IPV6_PRE96_UDP ( \
+ ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_L3_PRE96)
+
+#define ETH_RSS_IPV6_PRE32_TCP ( \
+ ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_L3_PRE32)
+
+#define ETH_RSS_IPV6_PRE40_TCP ( \
+ ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_L3_PRE40)
+
+#define ETH_RSS_IPV6_PRE48_TCP ( \
+ ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_L3_PRE48)
+
+#define ETH_RSS_IPV6_PRE56_TCP ( \
+ ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_L3_PRE56)
+
+#define ETH_RSS_IPV6_PRE64_TCP ( \
+ ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_L3_PRE64)
+
+#define ETH_RSS_IPV6_PRE96_TCP ( \
+ ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_L3_PRE96)
+
+#define ETH_RSS_IPV6_PRE32_SCTP ( \
+ ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_L3_PRE32)
+
+#define ETH_RSS_IPV6_PRE40_SCTP ( \
+ ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_L3_PRE40)
+
+#define ETH_RSS_IPV6_PRE48_SCTP ( \
+ ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_L3_PRE48)
+
+#define ETH_RSS_IPV6_PRE56_SCTP ( \
+ ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_L3_PRE56)
+
+#define ETH_RSS_IPV6_PRE64_SCTP ( \
+ ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_L3_PRE64)
+
+#define ETH_RSS_IPV6_PRE96_SCTP ( \
+ ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_L3_PRE96)
+
#define ETH_RSS_IP ( \
ETH_RSS_IPV4 | \
ETH_RSS_FRAG_IPV4 | \
ETH_RSS_GENEVE | \
ETH_RSS_NVGRE)
+#define ETH_RSS_VLAN ( \
+ ETH_RSS_S_VLAN | \
+ ETH_RSS_C_VLAN)
+
/**< Mask of valid RSS hash protocols */
#define ETH_RSS_PROTO_MASK ( \
ETH_RSS_IPV4 | \
/**< If set, reject sending out untagged pkts */
hw_vlan_insert_pvid : 1;
/**< If set, enable port based VLAN insertion */
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
* fields on rte_eth_dev_info structure are allowed to be set.
*/
uint64_t offloads;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
* fields on rte_eth_dev_info structure are allowed to be set.
*/
uint64_t offloads;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
#define DEV_RX_OFFLOAD_KEEP_CRC 0x00010000
#define DEV_RX_OFFLOAD_SCTP_CKSUM 0x00020000
#define DEV_RX_OFFLOAD_OUTER_UDP_CKSUM 0x00040000
+#define DEV_RX_OFFLOAD_RSS_HASH 0x00080000
#define DEV_RX_OFFLOAD_CHECKSUM (DEV_RX_OFFLOAD_IPV4_CKSUM | \
DEV_RX_OFFLOAD_UDP_CKSUM | \
#define DEV_TX_OFFLOAD_IP_TNL_TSO 0x00080000
/** Device supports outer UDP checksum */
#define DEV_TX_OFFLOAD_OUTER_UDP_CKSUM 0x00100000
-/**
- * Device supports match on metadata Tx offload..
- * Application must set PKT_TX_METADATA and mbuf metadata field.
- */
-#define DEV_TX_OFFLOAD_MATCH_METADATA 0x00200000
+
+/** Device supports send on timestamp */
+#define DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP 0x00200000
+
#define RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP 0x00000001
/**< Device supports Rx queue setup after device started*/
* Default values for switch domain id when ethdev does not support switch
* domain definitions.
*/
-#define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID (0)
+#define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID (UINT16_MAX)
/**
* Ethernet device associated switch information
const uint32_t *dev_flags; /**< Device flags */
uint32_t min_rx_bufsize; /**< Minimum size of RX buffer. */
uint32_t max_rx_pktlen; /**< Maximum configurable length of RX pkt. */
+ /** Maximum configurable size of LRO aggregated packet. */
+ uint32_t max_lro_pkt_size;
uint16_t max_rx_queues; /**< Maximum number of RX queues. */
uint16_t max_tx_queues; /**< Maximum number of TX queues. */
uint32_t max_mac_addrs; /**< Maximum number of MAC addresses. */
* embedded managed interconnect/switch.
*/
struct rte_eth_switch_info switch_info;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
uint16_t nb_desc; /**< configured number of TXDs. */
} __rte_cache_min_aligned;
+/* Generic Burst mode flag definition, values can be ORed. */
+
/**
- * Burst mode types, values can be ORed to define the burst mode of a driver.
+ * If the queues have different burst mode description, this bit will be set
+ * by PMD, then the application can iterate to retrieve burst description for
+ * all other queues.
*/
-enum rte_eth_burst_mode_option {
- RTE_ETH_BURST_SCALAR = (1 << 0),
- RTE_ETH_BURST_VECTOR = (1 << 1),
-
- /**< bits[15:2] are reserved for each vector type */
- RTE_ETH_BURST_ALTIVEC = (1 << 2),
- RTE_ETH_BURST_NEON = (1 << 3),
- RTE_ETH_BURST_SSE = (1 << 4),
- RTE_ETH_BURST_AVX2 = (1 << 5),
- RTE_ETH_BURST_AVX512 = (1 << 6),
-
- RTE_ETH_BURST_SCATTERED = (1 << 16), /**< Support scattered packets */
- RTE_ETH_BURST_BULK_ALLOC = (1 << 17), /**< Support mbuf bulk alloc */
- RTE_ETH_BURST_SIMPLE = (1 << 18),
-
- RTE_ETH_BURST_PER_QUEUE = (1 << 19), /**< Support per queue burst */
-};
+#define RTE_ETH_BURST_FLAG_PER_QUEUE (1ULL << 0)
/**
* Ethernet device RX/TX queue packet burst mode information structure.
* Used to retrieve information about packet burst mode setting.
*/
struct rte_eth_burst_mode {
- uint64_t options;
+ uint64_t flags; /**< The ORed values of RTE_ETH_BURST_FLAG_xxx */
+
+#define RTE_ETH_BURST_MODE_INFO_SIZE 1024 /**< Maximum size for information */
+ char info[RTE_ETH_BURST_MODE_INFO_SIZE]; /**< burst mode information */
};
/** Maximum name length for extended statistics counters */
*/
int rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,
uint32_t *ptypes, int num);
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Inform Ethernet device about reduced range of packet types to handle.
+ *
+ * Application can use this function to set only specific ptypes that it's
+ * interested. This information can be used by the PMD to optimize Rx path.
+ *
+ * The function accepts an array `set_ptypes` allocated by the caller to
+ * store the packet types set by the driver, the last element of the array
+ * is set to RTE_PTYPE_UNKNOWN. The size of the `set_ptype` array should be
+ * `rte_eth_dev_get_supported_ptypes() + 1` else it might only be filled
+ * partially.
+ *
+ * @param port_id
+ * The port identifier of the Ethernet device.
+ * @param ptype_mask
+ * The ptype family that application is interested in should be bitwise OR of
+ * RTE_PTYPE_*_MASK or 0.
+ * @param set_ptypes
+ * An array pointer to store set packet types, allocated by caller. The
+ * function marks the end of array with RTE_PTYPE_UNKNOWN.
+ * @param num
+ * Size of the array pointed by param ptypes.
+ * Should be rte_eth_dev_get_supported_ptypes() + 1 to accommodate the
+ * set ptypes.
+ * @return
+ * - (0) if Success.
+ * - (-ENODEV) if *port_id* invalid.
+ * - (-EINVAL) if *ptype_mask* is invalid (or) set_ptypes is NULL and
+ * num > 0.
+ */
+__rte_experimental
+int rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask,
+ uint32_t *set_ptypes, unsigned int num);
/**
* Retrieve the MTU of an Ethernet device.
RTE_ETH_EVENT_NEW, /**< port is probed */
RTE_ETH_EVENT_DESTROY, /**< port is released */
RTE_ETH_EVENT_IPSEC, /**< IPsec offload related event */
+ RTE_ETH_EVENT_FLOW_AGED,/**< New aged-out flows is detected */
RTE_ETH_EVENT_MAX /**< max value of this enum */
};
int rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
struct rte_eth_burst_mode *mode);
-/**
- * Retrieve name about burst mode option.
- *
- * @param option
- * The burst mode option of type *rte_eth_burst_mode_option*.
- *
- * @return
- * - "": Not found
- * - "xxx": name of the mode option.
- */
-__rte_experimental
-const char *
-rte_eth_burst_mode_option_name(uint64_t option);
-
/**
* Retrieve device registers and register attributes (number of registers and
* register size)
}
#endif
+ rte_ethdev_trace_rx_burst(port_id, queue_id, (void **)rx_pkts, nb_rx);
return nb_rx;
}
}
#endif
+ rte_ethdev_trace_tx_burst(port_id, queue_id, (void **)tx_pkts,
+ nb_pkts);
return (*dev->tx_pkt_burst)(dev->data->tx_queues[queue_id], tx_pkts, nb_pkts);
}