rte_eth_dev_mac_addr_add;
rte_eth_dev_mac_addr_remove;
rte_eth_dev_priority_flow_ctrl_set;
+ rte_eth_dev_release_port;
rte_eth_dev_rss_hash_conf_get;
rte_eth_dev_rss_hash_update;
rte_eth_dev_rss_reta_query;
local: *;
};
+
+DPDK_2.1 {
+ global:
+
+ rte_eth_dev_default_mac_addr_set;
+ rte_eth_dev_get_eeprom;
+ rte_eth_dev_get_eeprom_length;
+ rte_eth_dev_get_reg_info;
+ rte_eth_dev_get_reg_length;
+ rte_eth_dev_is_valid_port;
+ rte_eth_dev_rx_intr_ctl;
+ rte_eth_dev_rx_intr_ctl_q;
+ rte_eth_dev_rx_intr_disable;
+ rte_eth_dev_rx_intr_enable;
+ rte_eth_dev_set_eeprom;
+ rte_eth_dev_set_mc_addr_list;
+ rte_eth_timesync_disable;
+ rte_eth_timesync_enable;
+ rte_eth_timesync_read_rx_timestamp;
+ rte_eth_timesync_read_tx_timestamp;
+
+} DPDK_2.0;
+
+DPDK_2.2 {
+ global:
+
+ rte_eth_dev_get_dcb_info;
+ rte_eth_rx_queue_info_get;
+ rte_eth_tx_queue_info_get;
+
+} DPDK_2.1;