/*******************************************************************************
-Copyright (c) 2001-2012, Intel Corporation
+Copyright (c) 2001-2014, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
#include "e1000_api.h"
-STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
-STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
-STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
-static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
-static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
-static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
-static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
-static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
-static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
-static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
-static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
+STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
+STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
+STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
+STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
+STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
+STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
+STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
bool active);
STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
bool active);
-static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
-static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
+STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data);
STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
}
/* Ensure that the inter-port SWSM.SMBI lock bit is clear before
- * first NVM or PHY acess. This should be done for single-port
+ * first NVM or PHY access. This should be done for single-port
* devices, and for one port only on dual-port devices so that
* for those devices we can still use the SMBI lock to synchronize
* inter-port accesses to the PHY & NVM.
* Reads the PHY registers and stores the PHY ID and possibly the PHY
* revision in the hardware structure.
**/
-static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
+STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
*
* Acquire the HW semaphore to access the PHY or NVM
**/
-static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
+STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
{
u32 swsm;
s32 sw_timeout = hw->nvm.word_size + 1;
*
* Release hardware semaphore used to access the PHY or NVM
**/
-static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
+STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
{
u32 swsm;
* Acquire the HW semaphore during reset.
*
**/
-static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
+STATIC s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
{
u32 extcnf_ctrl;
s32 i = 0;
DEBUGFUNC("e1000_get_hw_semaphore_82573");
extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
- extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
do {
+ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
break;
- extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
msec_delay(2);
i++;
} while (i < MDIO_OWNERSHIP_TIMEOUT);
* Release hardware semaphore used during reset.
*
**/
-static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
+STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
{
u32 extcnf_ctrl;
* Acquire the HW semaphore to access the PHY or NVM.
*
**/
-static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
+STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
{
s32 ret_val;
* Release hardware semaphore used to access the PHY or NVM
*
**/
-static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
+STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
{
DEBUGFUNC("e1000_put_hw_semaphore_82574");
* If e1000_update_nvm_checksum is not called after this function, the
* EEPROM will most likely contain an invalid checksum.
**/
-static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data)
{
struct e1000_nvm_info *nvm = &hw->nvm;
}
for (i = 0; i < words; i++) {
- eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
- ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
- E1000_NVM_RW_REG_START;
+ eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
+ ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
+ E1000_NVM_RW_REG_START);
ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
if (ret_val)
/* When LPLU is enabled, we should disable SmartSpeed */
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
&data);
+ if (ret_val)
+ return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
data);
default:
break;
}
- if (ret_val)
- DEBUGOUT("Cannot acquire MDIO ownership\n");
ctrl = E1000_READ_REG(hw, E1000_CTRL);
/* Must release MDIO ownership and mutex after MAC reset. */
switch (hw->mac.type) {
+ case e1000_82573:
+ /* Release mutex only if the hw semaphore is acquired */
+ if (!ret_val)
+ e1000_put_hw_semaphore_82573(hw);
+ break;
case e1000_82574:
case e1000_82583:
- e1000_put_hw_semaphore_82574(hw);
+ /* Release mutex only if the hw semaphore is acquired */
+ if (!ret_val)
+ e1000_put_hw_semaphore_82574(hw);
break;
default:
break;
/* Initialize identification LED */
ret_val = mac->ops.id_led_init(hw);
+ /* An error is not fatal and we should not stop init due to this */
if (ret_val)
DEBUGOUT("Error initializing identification LED\n");
- /* This is not fatal and we should not stop init due to this */
/* Disabling VLAN filtering */
DEBUGOUT("Initializing the IEEE VLAN\n");
/* Set the transmit descriptor write-back policy */
reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
- reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
- E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+ reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
+ E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
/* ...for both queues. */
break;
default:
reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
- reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
- E1000_TXDCTL_FULL_TX_DESC_WB |
- E1000_TXDCTL_COUNT_DESC;
+ reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
+ E1000_TXDCTL_FULL_TX_DESC_WB |
+ E1000_TXDCTL_COUNT_DESC);
E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
break;
}
*
* Initializes required hardware-dependent bits needed for normal operation.
**/
-static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
+STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
{
u32 reg;
{
u16 status_1kbt = 0;
u16 receive_errors = 0;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_check_phy_82574");
ctrl = E1000_READ_REG(hw, E1000_CTRL);
status = E1000_READ_REG(hw, E1000_STATUS);
- rxcw = E1000_READ_REG(hw, E1000_RXCW);
+ E1000_READ_REG(hw, E1000_RXCW);
/* SYNCH bit and IV bit are sticky */
usec_delay(10);
rxcw = E1000_READ_REG(hw, E1000_RXCW);
if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
-
/* Receiver is synchronized with no invalid bits. */
switch (mac->serdes_link_state) {
case e1000_serdes_link_autoneg_complete:
* the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
* we need to return bad checksum.
**/
-static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
+STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
s32 ret_val;
if (ret_val)
return ret_val;
ret_val = nvm->ops.update(hw);
+ if (ret_val)
+ return ret_val;
}
}
DEBUGFUNC("e1000_read_mac_addr_82571");
if (hw->mac.type == e1000_82571) {
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
/* If there's an alternate MAC address place it in RAR0
* so that it will override the Si installed default perm
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