/*******************************************************************************
-Copyright (c) 2013 - 2014, Intel Corporation
+Copyright (c) 2013 - 2015, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
#define I40E_IEEE_ETS_PRIO_1_SHIFT 4
#define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
+#define I40E_CEE_PGID_PRIO_0_SHIFT 0
+#define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
+#define I40E_CEE_PGID_PRIO_1_SHIFT 4
+#define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
+#define I40E_CEE_PGID_STRICT 15
/* Defines for IEEE TSA types */
#define I40E_IEEE_TSA_STRICT 0
#define I40E_IEEE_APP_PRIO_SHIFT 5
#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
+/* TLV definitions for preparing MIB */
+#define I40E_TLV_ID_CHASSIS_ID 0
+#define I40E_TLV_ID_PORT_ID 1
+#define I40E_TLV_ID_TIME_TO_LIVE 2
+#define I40E_IEEE_TLV_ID_ETS_CFG 3
+#define I40E_IEEE_TLV_ID_ETS_REC 4
+#define I40E_IEEE_TLV_ID_PFC_CFG 5
+#define I40E_IEEE_TLV_ID_APP_PRI 6
+#define I40E_TLV_ID_END_OF_LLDPPDU 7
+#define I40E_TLV_ID_START I40E_IEEE_TLV_ID_ETS_CFG
+
+#define I40E_IEEE_ETS_TLV_LENGTH 25
+#define I40E_IEEE_PFC_TLV_LENGTH 6
+#define I40E_IEEE_APP_TLV_LENGTH 11
#pragma pack(1)
u32 deftsaassignment;
};
-#ifdef I40E_DCB_SW
-/* Data structures to pass for SW DCBX */
-struct i40e_rx_pb_config {
- u32 shared_pool_size;
- u32 shared_pool_high_wm;
- u32 shared_pool_low_wm;
- u32 shared_pool_high_thresh[I40E_MAX_TRAFFIC_CLASS];
- u32 shared_pool_low_thresh[I40E_MAX_TRAFFIC_CLASS];
- u32 tc_pool_size[I40E_MAX_TRAFFIC_CLASS];
- u32 tc_pool_high_wm[I40E_MAX_TRAFFIC_CLASS];
- u32 tc_pool_low_wm[I40E_MAX_TRAFFIC_CLASS];
-};
-
-enum i40e_dcb_arbiter_mode {
- I40E_DCB_ARB_MODE_STRICT_PRIORITY = 0,
- I40E_DCB_ARB_MODE_ROUND_ROBIN = 1
-};
-
-#define I40E_DEFAULT_PAUSE_TIME 0xffff
-#define I40E_MAX_FRAME_SIZE 4608 /* 4.5 KB */
-
-#define I40E_DEVICE_RPB_SIZE 968000 /* 968 KB */
-
-/* BitTimes (BT) conversion */
-#define I40E_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
-#define I40E_B2BT(BT) (BT * 8)
-#define I40E_BT2B(BT) ((BT + (8 - 1)) / (8))
-
-/* Max Frame(TC) = MFS(max) + MFS(TC) */
-#define I40E_MAX_FRAME_TC(mfs_max, mfs_tc) I40E_B2BT(mfs_max + mfs_tc)
-
-/* EEE Tx LPI Exit time in Bit Times */
-#define I40E_EEE_TX_LPI_EXIT_TIME 142500
-
-/* PCI Round Trip Time in Bit Times */
-#define I40E_PCIRTT_LINK_SPEED_10G 20000
-#define I40E_PCIRTT_BYTE_LINK_SPEED_20G 40000
-#define I40E_PCIRTT_BYTE_LINK_SPEED_40G 80000
-
-/* PFC Frame Delay Bit Times */
-#define I40E_PFC_FRAME_DELAY 672
-
-/* Worst case Cable (10GBase-T) Delay Bit Times */
-#define I40E_CABLE_DELAY 5556
-
-/* Higher Layer Delay @10G Bit Times */
-#define I40E_HIGHER_LAYER_DELAY_10G 6144
-
-/* Interface Delays in Bit Times */
-/* TODO: Add for other link speeds 20G/40G/etc. */
-#define I40E_INTERFACE_DELAY_10G_MAC_CONTROL 8192
-#define I40E_INTERFACE_DELAY_10G_MAC 8192
-#define I40E_INTERFACE_DELAY_10G_RS 8192
-
-#define I40E_INTERFACE_DELAY_XGXS 2048
-#define I40E_INTERFACE_DELAY_XAUI 2048
-
-#define I40E_INTERFACE_DELAY_10G_BASEX_PCS 2048
-#define I40E_INTERFACE_DELAY_10G_BASER_PCS 3584
-#define I40E_INTERFACE_DELAY_LX4_PMD 512
-#define I40E_INTERFACE_DELAY_CX4_PMD 512
-#define I40E_INTERFACE_DELAY_SERIAL_PMA 512
-#define I40E_INTERFACE_DELAY_PMD 512
-
-#define I40E_INTERFACE_DELAY_10G_BASET 25600
-
-/* delay values for with 10G BaseT in Bit Times */
-#define I40E_INTERFACE_DELAY_10G_COPPER \
- (I40E_INTERFACE_DELAY_10G_MAC + (2 * I40E_INTERFACE_DELAY_XAUI) \
- + I40E_INTERFACE_DELAY_10G_BASET)
-#define I40E_DV_TC(mfs_max, mfs_tc) \
- ((2 * I40E_MAX_FRAME_TC(mfs_max, mfs_tc)) \
- + I40E_PFC_FRAME_DELAY \
- + (2 * I40E_CABLE_DELAY) \
- + (2 * I40E_INTERFACE_DELAY_10G_COPPER) \
- + I40E_HIGHER_LAYER_DELAY_10G)
-#define I40E_STD_DV_TC(mfs_max, mfs_tc) \
- (I40E_DV_TC(mfs_max, mfs_tc) + I40E_B2BT(mfs_max))
-
-enum i40e_status_code i40e_process_lldp_event(struct i40e_hw *hw,
- struct i40e_arq_event_info *e);
-/* APIs for SW DCBX */
-void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,
- enum i40e_dcb_arbiter_mode ets_mode,
- enum i40e_dcb_arbiter_mode non_ets_mode,
- u32 max_exponent, u8 lltc_map);
-void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,
- u8 num_tc, u8 num_ports);
-void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,
- u8 pfc_en, u8 *prio_tc);
-void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc);
-u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw);
-void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,
- u8 *mode, u8 *prio_type);
-void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc);
-void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,
- u8 num_ports, bool eee_enabled,
- u8 pfc_en, u32 *mfs_tc,
- struct i40e_rx_pb_config *pb_cfg);
-void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,
- struct i40e_rx_pb_config *old_pb_cfg,
- struct i40e_rx_pb_config *new_pb_cfg);
-#endif /* I40E_DCB_SW */
enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw,
u16 *status);
enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,
struct i40e_dcbx_config *dcbcfg);
enum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw);
enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw);
+
#endif /* _I40E_DCB_H_ */
git.droids-corp.org / dpdk.git / blobdiff