/*-
* BSD LICENSE
*
- * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
static void i40e_configure_registers(struct i40e_hw *hw);
static void i40e_hw_init(struct i40e_hw *hw);
-static struct rte_pci_id pci_id_i40e_map[] = {
+static const struct rte_pci_id pci_id_i40e_map[] = {
#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "rte_pci_dev_ids.h"
{ .vendor_id = 0, /* sentinel */ },
};
-static struct eth_dev_ops i40e_eth_dev_ops = {
+static const struct eth_dev_ops i40e_eth_dev_ops = {
.dev_configure = i40e_dev_configure,
.dev_start = i40e_dev_start,
.dev_stop = i40e_dev_stop,
I40E_LINK_SPEED_100MB;
int ret = -ENOTSUP;
+ /* Skip it on 40G interfaces, as a workaround for the link issue */
+ if (i40e_is_40G_device(hw->device_id))
+ return I40E_SUCCESS;
+
status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
NULL);
if (status)
int
i40e_dev_link_update(struct rte_eth_dev *dev,
- __rte_unused int wait_to_complete)
+ int wait_to_complete)
{
+#define CHECK_INTERVAL 100 /* 100ms */
+#define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct i40e_link_status link_status;
struct rte_eth_link link, old;
int status;
+ unsigned rep_cnt = MAX_REPEAT_TIME;
memset(&link, 0, sizeof(link));
memset(&old, 0, sizeof(old));
memset(&link_status, 0, sizeof(link_status));
rte_i40e_dev_atomic_read_link_status(dev, &old);
- /* Get link status information from hardware */
- status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
- if (status != I40E_SUCCESS) {
- link.link_speed = ETH_LINK_SPEED_100;
- link.link_duplex = ETH_LINK_FULL_DUPLEX;
- PMD_DRV_LOG(ERR, "Failed to get link info");
- goto out;
- }
+ do {
+ /* Get link status information from hardware */
+ status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
+ if (status != I40E_SUCCESS) {
+ link.link_speed = ETH_LINK_SPEED_100;
+ link.link_duplex = ETH_LINK_FULL_DUPLEX;
+ PMD_DRV_LOG(ERR, "Failed to get link info");
+ goto out;
+ }
+
+ link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
+ if (!wait_to_complete)
+ break;
- link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
+ rte_delay_ms(CHECK_INTERVAL);
+ } while (!link.link_status && rep_cnt--);
if (!link.link_status)
goto out;
I40E_GLPRT_BPTCL(hw->port),
pf->offset_loaded, &os->eth.tx_broadcast,
&ns->eth.tx_broadcast);
- i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
- pf->offset_loaded, &os->eth.tx_discards,
- &ns->eth.tx_discards);
/* GLPRT_TEPC not supported */
/* additional port specific stats */
ctxt.connection_type = 0x1;
ctxt.flags = I40E_AQ_VSI_TYPE_VF;
- /* Configure switch ID */
- ctxt.info.valid_sections |=
- rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
- ctxt.info.switch_id =
- rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
+ /**
+ * Do not configure switch ID to enable VEB switch by
+ * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
+ * if the source mac address of packet sent from VF is not
+ * listed in the VEB's mac table, the VEB will switch the
+ * packet back to the VF. Need to enable it when HW issue
+ * is fixed.
+ */
+
/* Configure port/vlan */
ctxt.info.valid_sections |=
rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
ctxt.info.valid_sections |=
rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
} else if (type == I40E_VSI_FDIR) {
+ memset(&ctxt, 0, sizeof(ctxt));
vsi->uplink_seid = uplink_vsi->uplink_seid;
ctxt.pf_num = hw->pf_id;
ctxt.vf_num = 0;
if (vsi->type != I40E_VSI_MAIN) {
ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
- if (ret) {
+ if (ret != I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
hw->aq.asq_last_status);
goto fail_msix_alloc;
return flowtype_table[pctype];
}
-static int
-i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t *val)
-{
- struct i40e_aq_desc desc;
- enum i40e_status_code status;
-
- i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
- desc.params.internal.param1 = rte_cpu_to_le_32(addr);
- status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
- if (status < 0)
- return status;
-
- *val = ((uint64_t)(rte_le_to_cpu_32(desc.params.internal.param2)) <<
- (CHAR_BIT * sizeof(uint32_t))) +
- rte_le_to_cpu_32(desc.params.internal.param3);
-
- return status;
-}
-
/*
* On X710, performance number is far from the expectation on recent firmware
* versions; on XL710, performance number is also far from the expectation on
I40E_GL_SWR_PM_UP_THR_EF_VALUE;
}
- ret = i40e_debug_read_register(hw, reg_table[i].addr, ®);
+ ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
+ ®, NULL);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
reg_table[i].addr);
git.droids-corp.org / dpdk.git / blobdiff