ixgbe: make register maps const

[dpdk.git] / lib / librte_pmd_i40e / i40e_ethdev.h

diff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h
index ceda53a..b9bed5a 100644 (file)
--- a/lib/librte_pmd_i40e/i40e_ethdev.h
+++ b/lib/librte_pmd_i40e/i40e_ethdev.h
@@ -50,6 +50,15 @@
 #define I40E_DEFAULT_QP_NUM_FDIR  1
 #define I40E_UINT32_BIT_SIZE      (CHAR_BIT * sizeof(uint32_t))
 #define I40E_VFTA_SIZE            (4096 / I40E_UINT32_BIT_SIZE)
+/*
+ * vlan_id is a 12 bit number.
+ * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
+ * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
+ * The higher 7 bit val specifies VFTA array index.
+ */
+#define I40E_VFTA_BIT(vlan_id)    (1 << ((vlan_id) & 0x1F))
+#define I40E_VFTA_IDX(vlan_id)    ((vlan_id) >> 5)
+
 /* Default TC traffic in case DCB is not enabled */
 #define I40E_DEFAULT_TCMAP        0x1
 #define I40E_FDIR_QUEUE_ID        0
@@ -80,6 +89,18 @@
 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
 #define I40E_48_BIT_MASK  RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
 
+/* index flex payload per layer */
+enum i40e_flxpld_layer_idx {
+       I40E_FLXPLD_L2_IDX    = 0,
+       I40E_FLXPLD_L3_IDX    = 1,
+       I40E_FLXPLD_L4_IDX    = 2,
+       I40E_MAX_FLXPLD_LAYER = 3,
+};
+#define I40E_MAX_FLXPLD_FIED        3  /* max number of flex payload fields */
+#define I40E_FDIR_BITMASK_NUM_WORD  2  /* max number of bitmask words */
+#define I40E_FDIR_MAX_FLEXWORD_NUM  8  /* max number of flexpayload words */
+#define I40E_FDIR_MAX_FLEX_LEN      16 /* len in bytes of flex payload */
+
 /* i40e flags */
 #define I40E_FLAG_RSS                   (1ULL << 0)
 #define I40E_FLAG_DCB                   (1ULL << 1)
@@ -99,16 +120,16 @@
                       I40E_FLAG_VXLAN)
 
 #define I40E_RSS_OFFLOAD_ALL ( \
-       ETH_RSS_NONF_IPV4_UDP | \
-       ETH_RSS_NONF_IPV4_TCP | \
-       ETH_RSS_NONF_IPV4_SCTP | \
-       ETH_RSS_NONF_IPV4_OTHER | \
        ETH_RSS_FRAG_IPV4 | \
-       ETH_RSS_NONF_IPV6_UDP | \
-       ETH_RSS_NONF_IPV6_TCP | \
-       ETH_RSS_NONF_IPV6_SCTP | \
-       ETH_RSS_NONF_IPV6_OTHER | \
+       ETH_RSS_NONFRAG_IPV4_TCP | \
+       ETH_RSS_NONFRAG_IPV4_UDP | \
+       ETH_RSS_NONFRAG_IPV4_SCTP | \
+       ETH_RSS_NONFRAG_IPV4_OTHER | \
        ETH_RSS_FRAG_IPV6 | \
+       ETH_RSS_NONFRAG_IPV6_TCP | \
+       ETH_RSS_NONFRAG_IPV6_UDP | \
+       ETH_RSS_NONFRAG_IPV6_SCTP | \
+       ETH_RSS_NONFRAG_IPV6_OTHER | \
        ETH_RSS_L2_PAYLOAD)
 
 /* All bits of RSS hash enable */
@@ -266,6 +287,24 @@ struct i40e_vmdq_info {
        struct i40e_vsi *vsi;
 };
 
+/*
+ * Structure to store flex pit for flow diretor.
+ */
+struct i40e_fdir_flex_pit {
+       uint8_t src_offset;    /* offset in words from the beginning of payload */
+       uint8_t size;          /* size in words */
+       uint8_t dst_offset;    /* offset in words of flexible payload */
+};
+
+struct i40e_fdir_flex_mask {
+       uint8_t word_mask;  /**< Bit i enables word i of flexible payload */
+       struct {
+               uint8_t offset;
+               uint16_t mask;
+       } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
+};
+
+#define I40E_FILTER_PCTYPE_MAX 64
 /*
  *  A structure used to define fields of a FDIR related info.
  */
@@ -276,6 +315,12 @@ struct i40e_fdir_info {
        struct i40e_rx_queue *rxq;
        void *prg_pkt;                 /* memory for fdir program packet */
        uint64_t dma_addr;             /* physic address of packet memory*/
+       /*
+        * the rule how bytes stream is extracted as flexible payload
+        * for each payload layer, the setting can up to three elements
+        */
+       struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
+       struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
 };
 
 /*
@@ -425,6 +470,12 @@ const struct rte_memzone *i40e_memzone_reserve(const char *name,
                                        uint32_t len,
                                        int socket_id);
 int i40e_fdir_configure(struct rte_eth_dev *dev);
+void i40e_fdir_teardown(struct i40e_pf *pf);
+enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
+uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
+int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
+                         enum rte_filter_op filter_op,
+                         void *arg);
 
 /* I40E_DEV_PRIVATE_TO */
 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
@@ -487,4 +538,30 @@ i40e_init_adminq_parameter(struct i40e_hw *hw)
        hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
 }
 
+#define I40E_VALID_FLOW(flow_type) \
+       ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
+       (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
+       (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
+       (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
+
+#define I40E_VALID_PCTYPE(pctype) \
+       ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
+       (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
+       (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
+
 #endif /* _I40E_ETHDEV_H_ */