ixgbe/base: flow director changes

[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_82599.c

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
index 13fa4da..8bc5320 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
@@ -1464,8 +1464,10 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
  *  @hw: pointer to hardware structure
  *  @fdirctrl: value to write to flow director control register, initially
  *          contains just the value of the Rx packet buffer allocation
+ *  @cloud_mode: true - cloude mode, false - other mode
  **/
-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
+                       bool cloud_mode)
 {
        DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
 
@@ -1662,34 +1664,20 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 
        u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
        u32 bucket_hash = 0;
+       u32 hi_dword = 0;
+       u32 i = 0;
 
        /* Apply masks to input data */
-       input->dword_stream[0]  &= input_mask->dword_stream[0];
-       input->dword_stream[1]  &= input_mask->dword_stream[1];
-       input->dword_stream[2]  &= input_mask->dword_stream[2];
-       input->dword_stream[3]  &= input_mask->dword_stream[3];
-       input->dword_stream[4]  &= input_mask->dword_stream[4];
-       input->dword_stream[5]  &= input_mask->dword_stream[5];
-       input->dword_stream[6]  &= input_mask->dword_stream[6];
-       input->dword_stream[7]  &= input_mask->dword_stream[7];
-       input->dword_stream[8]  &= input_mask->dword_stream[8];
-       input->dword_stream[9]  &= input_mask->dword_stream[9];
-       input->dword_stream[10] &= input_mask->dword_stream[10];
+       for (i = 0; i < 14; i++)
+               input->dword_stream[i]  &= input_mask->dword_stream[i];
 
        /* record the flow_vm_vlan bits as they are a key part to the hash */
        flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
 
        /* generate common hash dword */
-       hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
-                                   input->dword_stream[2] ^
-                                   input->dword_stream[3] ^
-                                   input->dword_stream[4] ^
-                                   input->dword_stream[5] ^
-                                   input->dword_stream[6] ^
-                                   input->dword_stream[7] ^
-                                   input->dword_stream[8] ^
-                                   input->dword_stream[9] ^
-                                   input->dword_stream[10]);
+       for (i = 1; i <= 13; i++)
+               hi_dword ^= input->dword_stream[i];
+       hi_hash_dword = IXGBE_NTOHL(hi_dword);
 
        /* low dword is word swapped version of common */
        lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
@@ -1708,21 +1696,8 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
        lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 
        /* Process remaining 30 bit of the key */
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
+       for (i = 1; i <= 15; i++)
+               IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
 
        /*
         * Limit hash to 13 bits since max bucket count is 8K.
@@ -1769,7 +1744,7 @@ STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
        IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
 
 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
-                                   union ixgbe_atr_input *input_mask)
+                                   union ixgbe_atr_input *input_mask, bool cloud_mode)
 {
        /* mask IPv6 since it is currently not supported */
        u32 fdirm = IXGBE_FDIRM_DIPv6;
@@ -1868,7 +1843,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 
 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
                                          union ixgbe_atr_input *input,
-                                         u16 soft_id, u8 queue)
+                                         u16 soft_id, u8 queue, bool cloud_mode)
 {
        u32 fdirport, fdirvlan, fdirhash, fdircmd;
 
@@ -1917,6 +1892,8 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
                  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
        if (queue == IXGBE_FDIR_DROP_QUEUE)
                fdircmd |= IXGBE_FDIRCMD_DROP;
+       if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
+               fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
        fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
        fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
        fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
@@ -1983,7 +1960,7 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
                                        union ixgbe_atr_input *input,
                                        union ixgbe_atr_input *input_mask,
-                                       u16 soft_id, u8 queue)
+                                       u16 soft_id, u8 queue, bool cloud_mode)
 {
        s32 err = IXGBE_ERR_CONFIG;
 
@@ -1995,6 +1972,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
         */
        switch (input->formatted.flow_type) {
        case IXGBE_ATR_FLOW_TYPE_IPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
                input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
                if (input->formatted.dst_port || input->formatted.src_port) {
                        DEBUGOUT(" Error on src/dst port\n");
@@ -2002,12 +1980,15 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
                }
                break;
        case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
                if (input->formatted.dst_port || input->formatted.src_port) {
                        DEBUGOUT(" Error on src/dst port\n");
                        return IXGBE_ERR_CONFIG;
                }
        case IXGBE_ATR_FLOW_TYPE_TCPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
        case IXGBE_ATR_FLOW_TYPE_UDPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
                input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
                                                  IXGBE_ATR_L4TYPE_MASK;
                break;
@@ -2017,7 +1998,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
        }
 
        /* program input mask into the HW */
-       err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
+       err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
        if (err)
                return err;
 
@@ -2026,7 +2007,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
 
        /* program filters to filter memory */
        return ixgbe_fdir_write_perfect_filter_82599(hw, input,
-                                                    soft_id, queue);
+                                                    soft_id, queue, cloud_mode);
 }
 
 /**