ixgbe/base: minor changes

[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_82599.c

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
index 7d9decd..03a4b8c 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
@@ -1076,7 +1076,7 @@ mac_reset_top:
        IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
        IXGBE_WRITE_FLUSH(hw);
 
-       /* Poll for reset bit to self-clear indicating reset is complete */
+       /* Poll for reset bit to self-clear meaning reset is complete */
        for (i = 0; i < 10; i++) {
                usec_delay(1);
                ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
@@ -1093,8 +1093,8 @@ mac_reset_top:
 
        /*
         * Double resets are required for recovery from certain error
-        * conditions.  Between resets, it is necessary to stall to allow time
-        * for any pending HW events to complete.
+        * conditions.  Between resets, it is necessary to stall to
+        * allow time for any pending HW events to complete.
         */
        if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
                hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
@@ -1359,6 +1359,7 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
                    (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
                    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 
+
        /* write hashes and fdirctrl register, poll for completion */
        ixgbe_fdir_enable_82599(hw, fdirctrl);
 
@@ -1475,6 +1476,7 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
        /*
         * Get the flow_type in order to program FDIRCMD properly
         * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
+        * fifth is FDIRCMD.TUNNEL_FILTER
         */
        switch (input.formatted.flow_type) {
        case IXGBE_ATR_FLOW_TYPE_TCPV4:
@@ -1646,7 +1648,6 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
        /* mask IPv6 since it is currently not supported */
        u32 fdirm = IXGBE_FDIRM_DIPv6;
        u32 fdirtcpm;
-
        DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
 
        /*
@@ -1719,6 +1720,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
                return IXGBE_ERR_CONFIG;
        }
 
+
        /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
        IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 
@@ -1772,6 +1774,7 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
        fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
        IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
 
+
        /* configure FDIRHASH register */
        fdirhash = input->formatted.bkt_hash;
        fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
@@ -1987,7 +1990,7 @@ out:
  **/
 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
 {
-       s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
+       s32 status;
 
        DEBUGFUNC("ixgbe_identify_phy_82599");
 
@@ -2175,11 +2178,11 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
  *  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
  *  if the FW version is not supported.
  **/
-s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
+STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
 {
        s32 status = IXGBE_ERR_EEPROM_VERSION;
        u16 fw_offset, fw_ptp_cfg_offset;
-       u16 fw_version = 0;
+       u16 fw_version;
 
        DEBUGFUNC("ixgbe_verify_fw_version_82599");