ixgbe/base: extract management capability check

[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_common.c

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c
index 28eb3eb..ddf61cc 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c
@@ -4079,22 +4079,27 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
                        *link_up = false;
        }
 
-       if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-           IXGBE_LINKS_SPEED_10G_82599) {
+       switch (links_reg & IXGBE_LINKS_SPEED_82599) {
+       case IXGBE_LINKS_SPEED_10G_82599:
                *speed = IXGBE_LINK_SPEED_10GB_FULL;
-               if (hw->mac.type > ixgbe_mac_X550) {
+               if (hw->mac.type >= ixgbe_mac_X550) {
                        if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
                                *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
                }
-       }
-       else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-                IXGBE_LINKS_SPEED_1G_82599)
+               break;
+       case IXGBE_LINKS_SPEED_1G_82599:
                *speed = IXGBE_LINK_SPEED_1GB_FULL;
-       else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-                IXGBE_LINKS_SPEED_100_82599)
+               break;
+       case IXGBE_LINKS_SPEED_100_82599:
                *speed = IXGBE_LINK_SPEED_100_FULL;
-       else
+               if (hw->mac.type >= ixgbe_mac_X550) {
+                       if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
+                               *speed = IXGBE_LINK_SPEED_5GB_FULL;
+               }
+               break;
+       default:
                *speed = IXGBE_LINK_SPEED_UNKNOWN;
+       }
 
        return IXGBE_SUCCESS;
 }
@@ -4579,7 +4584,8 @@ void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
  **/
 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
 {
-       u32 gcr_ext, hlreg0;
+       u32 gcr_ext, hlreg0, i, poll;
+       u16 value;
 
        /*
         * If double reset is not requested then all transactions should
@@ -4596,6 +4602,25 @@ void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
        hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
        IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
 
+       /* Wait for a last completion before clearing buffers */
+       IXGBE_WRITE_FLUSH(hw);
+       msec_delay(3);
+
+       /*
+        * Before proceeding, make sure that the PCIe block does not have
+        * transactions pending.
+        */
+       poll = ixgbe_pcie_timeout_poll(hw);
+       for (i = 0; i < poll; i++) {
+               usec_delay(100);
+               value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
+               if (IXGBE_REMOVED(hw->hw_addr))
+                       goto out;
+               if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
+                       goto out;
+       }
+
+out:
        /* initiate cleaning flow for buffers in the PCIe transaction layer */
        gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
        IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
@@ -4838,6 +4863,22 @@ void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
        }
 }
 
+/**
+ * ixgbe_mng_present - returns true when management capability is present
+ * @hw: pointer to hardware structure
+ */
+bool ixgbe_mng_present(struct ixgbe_hw *hw)
+{
+       u32 fwsm;
+
+       if (hw->mac.type < ixgbe_mac_82599EB)
+               return false;
+
+       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
+       fwsm &= IXGBE_FWSM_MODE_MASK;
+       return fwsm == IXGBE_FWSM_FW_MODE_PT;
+}
+
 /**
  * ixgbe_mng_enabled - Is the manageability engine enabled?
  * @hw: pointer to hardware structure