ixgbe/base: fix mac type checks

[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_dcb_82599.c

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb_82599.c
index cc7ce7a..9778164 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb_82599.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb_82599.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 
-Copyright (c) 2001-2012, Intel Corporation
+Copyright (c) 2001-2014, Intel Corporation
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -35,7 +35,6 @@ POSSIBILITY OF SUCH DAMAGE.
 #include "ixgbe_type.h"
 #include "ixgbe_dcb.h"
 #include "ixgbe_dcb_82599.h"
-#ident "$Id: ixgbe_dcb_82599.c,v 1.67 2012/03/30 06:45:33 jtkirshe Exp $"
 
 /**
  * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
@@ -299,7 +298,7 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
         */
        reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
 
-       if (hw->mac.type == ixgbe_mac_X540)
+       if (hw->mac.type >= ixgbe_mac_X540)
                reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
 
        if (pfc_en)
@@ -329,7 +328,14 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
                        fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
                        IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
                } else {
-                       reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
+                       /*
+                        * In order to prevent Tx hangs when the internal Tx
+                        * switch is enabled we must set the high water mark
+                        * to the Rx packet buffer size - 24KB.  This allows
+                        * the Tx switch to function even under heavy Rx
+                        * workloads.
+                        */
+                       reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
                        IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
                }
 
@@ -573,6 +579,7 @@ s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
                              u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
                              u8 *map)
 {
+       UNREFERENCED_1PARAMETER(link_speed);
 
        ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
                                          map);