ixgbe/base: set X540 phy power

[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_type.h

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index 9a66370..376f00c 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -74,7 +74,6 @@ POSSIBILITY OF SUCH DAMAGE.
 
 #include "ixgbe_osdep.h"
 
-#ident "$Id: ixgbe_type.h,v 1.630 2013/11/22 22:48:40 jtkirshe Exp $"
 
 /* Vendor ID */
 #define IXGBE_INTEL_VENDOR_ID                  0x8086
@@ -188,6 +187,12 @@ POSSIBILITY OF SUCH DAMAGE.
                                        0x00001000 : 0x00000004)
 #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
                                        0x00000400 : 0x00000008)
+#define IXGBE_I2C_BB_EN_BY_MAC(hw) ((hw)->mac.type >= ixgbe_mac_X550 ? \
+                                   0x00000100 : 0)
+#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw) ((hw)->mac.type >= ixgbe_mac_X550 ? \
+                                          0x00000800 : 0)
+#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw) ((hw)->mac.type >= ixgbe_mac_X550 ? \
+                                         0x00002000 : 0)
 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT     500
 
 #define IXGBE_I2C_THERMAL_SENSOR_ADDR  0xF8
@@ -1410,6 +1415,8 @@ struct ixgbe_dmac_config {
 #define IXGBE_MII_10GBASE_T_ADVERTISE          0x1000 /* full duplex, bit:12*/
 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX    0x4000 /* full duplex, bit:14*/
 #define IXGBE_MII_1GBASE_T_ADVERTISE           0x8000 /* full duplex, bit:15*/
+#define IXGBE_MII_2_5GBASE_T_ADVERTISE         0x0400
+#define IXGBE_MII_5GBASE_T_ADVERTISE           0x0800
 #define IXGBE_MII_100BASE_T_ADVERTISE          0x0100 /* full duplex, bit:8 */
 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF     0x0080 /* half duplex, bit:7 */
 #define IXGBE_MII_RESTART                      0x200
@@ -1975,12 +1982,12 @@ enum {
 #define IXGBE_SWFW_REGSMP      0x80000000 /* Register Semaphore bit 31 */
 
 /* SW_FW_SYNC/GSSR definitions */
-#define IXGBE_GSSR_EEP_SM      0x0001
-#define IXGBE_GSSR_PHY0_SM     0x0002
-#define IXGBE_GSSR_PHY1_SM     0x0004
-#define IXGBE_GSSR_MAC_CSR_SM  0x0008
-#define IXGBE_GSSR_FLASH_SM    0x0010
-#define IXGBE_GSSR_SW_MNG_SM   0x0400
+#define IXGBE_GSSR_EEP_SM              0x0001
+#define IXGBE_GSSR_PHY0_SM             0x0002
+#define IXGBE_GSSR_PHY1_SM             0x0004
+#define IXGBE_GSSR_MAC_CSR_SM          0x0008
+#define IXGBE_GSSR_FLASH_SM            0x0010
+#define IXGBE_GSSR_SW_MNG_SM           0x0400
 #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
 #define IXGBE_GSSR_I2C_MASK    0x1800
 #define IXGBE_GSSR_NVM_PHY_MASK        0xF
@@ -2962,7 +2969,8 @@ typedef u32 ixgbe_link_speed;
 #define IXGBE_LINK_SPEED_UNKNOWN       0
 #define IXGBE_LINK_SPEED_100_FULL      0x0008
 #define IXGBE_LINK_SPEED_1GB_FULL      0x0020
-#define IXGBE_LINK_SPEED_2_5GB_FULL    0x0040
+#define IXGBE_LINK_SPEED_2_5GB_FULL    0x0400
+#define IXGBE_LINK_SPEED_5GB_FULL      0x0800
 #define IXGBE_LINK_SPEED_10GB_FULL     0x0080
 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
                                         IXGBE_LINK_SPEED_10GB_FULL)
@@ -3265,6 +3273,7 @@ enum ixgbe_bus_type {
        ixgbe_bus_type_pci,
        ixgbe_bus_type_pcix,
        ixgbe_bus_type_pci_express,
+       ixgbe_bus_type_internal,
        ixgbe_bus_type_reserved
 };
 
@@ -3539,6 +3548,7 @@ struct ixgbe_phy_operations {
        s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
        s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
        s32 (*check_overtemp)(struct ixgbe_hw *);
+       s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
 };
 
 struct ixgbe_eeprom_info {