ixgbe/base: reset VF registers

[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_type.h

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index fc3fc06..ef593f4 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 
-Copyright (c) 2001-2012, Intel Corporation
+Copyright (c) 2001-2014, Intel Corporation
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -74,7 +74,7 @@ POSSIBILITY OF SUCH DAMAGE.
 
 #include "ixgbe_osdep.h"
 
-#ident "$Id: ixgbe_type.h,v 1.552 2012/11/08 11:33:27 jtkirshe Exp $"
+#ident "$Id: ixgbe_type.h,v 1.630 2013/11/22 22:48:40 jtkirshe Exp $"
 
 /* Vendor ID */
 #define IXGBE_INTEL_VENDOR_ID                  0x8086
@@ -114,12 +114,14 @@ POSSIBILITY OF SUCH DAMAGE.
 #define IXGBE_DEV_ID_82599_SFP_EM              0x1507
 #define IXGBE_DEV_ID_82599_SFP_SF2             0x154D
 #define IXGBE_DEV_ID_82599_SFP_SF_QP           0x154A
+#define IXGBE_DEV_ID_82599_QSFP_SF_QP          0x1558
 #define IXGBE_DEV_ID_82599EN_SFP               0x1557
 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1       0x0001
 #define IXGBE_DEV_ID_82599_XAUI_LOM            0x10FC
 #define IXGBE_DEV_ID_82599_T3_LOM              0x151C
 #define IXGBE_DEV_ID_82599_VF                  0x10ED
 #define IXGBE_DEV_ID_82599_VF_HV               0x152E
+#define IXGBE_DEV_ID_82599_LS                  0x154F
 #define IXGBE_DEV_ID_X540T                     0x1528
 #define IXGBE_DEV_ID_X540_VF                   0x1515
 #define IXGBE_DEV_ID_X540_VF_HV                        0x1530
@@ -1815,6 +1817,9 @@ enum {
 #define IXGBE_GSSR_MAC_CSR_SM  0x0008
 #define IXGBE_GSSR_FLASH_SM    0x0010
 #define IXGBE_GSSR_SW_MNG_SM   0x0400
+#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
+#define IXGBE_GSSR_I2C_MASK    0x1800
+#define IXGBE_GSSR_NVM_PHY_MASK        0xF
 
 /* FW Status register bitmask */
 #define IXGBE_FWSTS_FWRI       0x00000200 /* Firmware Reset Indication */
@@ -2236,6 +2241,10 @@ enum {
 
 /* SRRCTL bit definitions */
 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT    10 /* so many KBs */
+#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT        2 /* 64byte resolution (>> 6)
+                                          * + at bit 8 offset (<< 8)
+                                          *  = (<< 2)
+                                          */
 #define IXGBE_SRRCTL_RDMTS_SHIFT       22
 #define IXGBE_SRRCTL_RDMTS_MASK                0x01C00000
 #define IXGBE_SRRCTL_DROP_EN           0x10000000
@@ -2834,6 +2843,10 @@ enum ixgbe_phy_type {
        ixgbe_phy_sfp_ftl_active,
        ixgbe_phy_sfp_unknown,
        ixgbe_phy_sfp_intel,
+       ixgbe_phy_qsfp_passive_unknown,
+       ixgbe_phy_qsfp_active_unknown,
+       ixgbe_phy_qsfp_intel,
+       ixgbe_phy_qsfp_unknown,
        ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
        ixgbe_phy_generic
 };
@@ -2865,14 +2878,8 @@ enum ixgbe_sfp_type {
        ixgbe_sfp_type_1g_cu_core1 = 10,
        ixgbe_sfp_type_1g_sx_core0 = 11,
        ixgbe_sfp_type_1g_sx_core1 = 12,
-#ifdef SUPPORT_1000BASE_LX
        ixgbe_sfp_type_1g_lx_core0 = 13,
        ixgbe_sfp_type_1g_lx_core1 = 14,
-#endif /* SUPPORT_1000BASE_LX */
-#ifdef SUPPORT_10GBASE_ER
-       ixgbe_sfp_type_er_core0 = 15,
-       ixgbe_sfp_type_er_core1 = 16,
-#endif /* SUPPORT_10GBASE_ER */
        ixgbe_sfp_type_not_present = 0xFFFE,
        ixgbe_sfp_type_unknown = 0xFFFF
 };
@@ -2880,6 +2887,8 @@ enum ixgbe_sfp_type {
 enum ixgbe_media_type {
        ixgbe_media_type_unknown = 0,
        ixgbe_media_type_fiber,
+       ixgbe_media_type_fiber_qsfp,
+       ixgbe_media_type_fiber_lco,
        ixgbe_media_type_copper,
        ixgbe_media_type_backplane,
        ixgbe_media_type_cx4,
@@ -3065,7 +3074,7 @@ struct ixgbe_eeprom_operations {
        s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
        s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
        s32 (*update_checksum)(struct ixgbe_hw *);
-       u16 (*calc_checksum)(struct ixgbe_hw *);
+       s32 (*calc_checksum)(struct ixgbe_hw *);
 };
 
 struct ixgbe_mac_operations {
@@ -3091,8 +3100,8 @@ struct ixgbe_mac_operations {
        s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
        s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
        s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
-       s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
-       void (*release_swfw_sync)(struct ixgbe_hw *, u16);
+       s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
+       void (*release_swfw_sync)(struct ixgbe_hw *, u32);
        s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
        s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
 
@@ -3225,12 +3234,15 @@ struct ixgbe_phy_info {
        bool sfp_setup_needed;
        u32 revision;
        enum ixgbe_media_type media_type;
+       u32 phy_semaphore_mask;
+       u8 lan_id;
        bool reset_disable;
        ixgbe_autoneg_advertised autoneg_advertised;
        enum ixgbe_smart_speed smart_speed;
        bool smart_speed_active;
        bool multispeed_fiber;
        bool reset_if_overtemp;
+       bool qsfp_shared_i2c_bus;
 };
 
 #include "ixgbe_mbx.h"
@@ -3327,6 +3339,7 @@ struct ixgbe_hw {
 #define IXGBE_ERR_OUT_OF_MEM                   -34
 #define IXGBE_ERR_FEATURE_NOT_SUPPORTED                -36
 #define IXGBE_ERR_EEPROM_PROTECTED_REGION      -37
+#define IXGBE_ERR_FDIR_CMD_INCOMPLETE          -38
 
 #define IXGBE_NOT_IMPLEMENTED                  0x7FFFFFFF