ixgbe/base: iosf sideband read/write

[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_vf.c

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c
index f576a51..e6b6c51 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 
-Copyright (c) 2001-2012, Intel Corporation
+Copyright (c) 2001-2014, Intel Corporation
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -35,7 +35,7 @@ POSSIBILITY OF SUCH DAMAGE.
 #include "ixgbe_api.h"
 #include "ixgbe_type.h"
 #include "ixgbe_vf.h"
-#ident "$Id: ixgbe_vf.c,v 1.58 2012/08/09 20:24:53 cmwyborn Exp $"
+#ident "$Id: ixgbe_vf.c,v 1.62 2013/06/27 21:30:59 jtkirshe Exp $"
 
 #ifndef IXGBE_VFWRITE_REG
 #define IXGBE_VFWRITE_REG IXGBE_WRITE_REG
@@ -89,6 +89,49 @@ s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)
        return IXGBE_SUCCESS;
 }
 
+/* ixgbe_virt_clr_reg - Set register to default (power on) state.
+ *  @hw: pointer to hardware structure
+ */
+static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)
+{
+       int i;
+       u32 vfsrrctl;
+       u32 vfdca_rxctrl;
+       u32 vfdca_txctrl;
+
+       /* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */
+       vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
+       vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
+
+       /* DCA_RXCTRL default value */
+       vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN |
+                      IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+                      IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
+
+       /* DCA_TXCTRL default value */
+       vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN |
+                      IXGBE_DCA_TXCTRL_DESC_WRO_EN |
+                      IXGBE_DCA_TXCTRL_DATA_RRO_EN;
+
+       IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
+
+       for (i = 0; i < 7; i++) {
+               IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl);
+               IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl);
+               IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl);
+       }
+
+       IXGBE_WRITE_FLUSH(hw);
+}
+
 /**
  *  ixgbe_start_hw_vf - Prepare hardware for Tx/Rx
  *  @hw: pointer to hardware structure
@@ -161,6 +204,9 @@ s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)
        if (!timeout)
                return IXGBE_ERR_RESET_FAILED;
 
+       /* Reset VF registers to initial values */
+       ixgbe_virt_clr_reg(hw);
+
        /* mailbox timeout can now become active */
        mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;
 
@@ -515,6 +561,21 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
        if (!(links_reg & IXGBE_LINKS_UP))
                goto out;
 
+       /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
+        * before the link status is correct
+        */
+       if (mac->type == ixgbe_mac_82599_vf) {
+               int i;
+
+               for (i = 0; i < 5; i++) {
+                       usec_delay(100);
+                       links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
+
+                       if (!(links_reg & IXGBE_LINKS_UP))
+                               goto out;
+               }
+       }
+
        switch (links_reg & IXGBE_LINKS_SPEED_82599) {
        case IXGBE_LINKS_SPEED_10G_82599:
                *speed = IXGBE_LINK_SPEED_10GB_FULL;