cryptodev: modify return value for asym session create

[dpdk.git] / lib / table / rte_swx_table_selector.h

diff --git a/lib/table/rte_swx_table_selector.h b/lib/table/rte_swx_table_selector.h
index 71b6a74..05863cc 100644 (file)
--- a/lib/table/rte_swx_table_selector.h
+++ b/lib/table/rte_swx_table_selector.h
@@ -16,7 +16,6 @@ extern "C" {
  */
 
 #include <stdint.h>
-#include <sys/queue.h>
 
 #include <rte_compat.h>
 
@@ -56,7 +55,7 @@ struct rte_swx_table_selector_params {
 /** Group member parameters. */
 struct rte_swx_table_selector_member {
        /** Linked list connectivity. */
-       TAILQ_ENTRY(rte_swx_table_selector_member) node;
+       RTE_TAILQ_ENTRY(rte_swx_table_selector_member) node;
 
        /** Member ID. */
        uint32_t member_id;
@@ -66,7 +65,7 @@ struct rte_swx_table_selector_member {
 };
 
 /** List of group members. */
-TAILQ_HEAD(rte_swx_table_selector_member_list, rte_swx_table_selector_member);
+RTE_TAILQ_HEAD(rte_swx_table_selector_member_list, rte_swx_table_selector_member);
 
 /** Group parameters. */
 struct rte_swx_table_selector_group {
@@ -156,7 +155,7 @@ rte_swx_table_selector_group_set(void *table,
  * mechanism allows for multiple concurrent select operations into the same table.
  *
  * The typical reason an implementation may choose to split the operation into multiple steps is to
- * hide the latency of the inherrent memory read operations: before a read operation with the
+ * hide the latency of the inherent memory read operations: before a read operation with the
  * source data likely not in the CPU cache, the source data prefetch is issued and the operation is
  * postponed in favor of some other unrelated work, which the CPU executes in parallel with the
  * source data being fetched into the CPU cache; later on, the operation is resumed, this time with